30

5387B–HIREL–07/05

PC7447A [Preliminary]

9.2.3

IEEE 1149.1 AC Timing Specifications

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-

tion. The output timings are measured at the pins. All output timings assume a purely resistive 50

Time-of-flight delays must be added for trace lengths, vias and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization

Figure 9-4.

Alternate AC Test Load for the JTAG Interface

Table 9-4.

Symbol

Parameter

Min

Max

Unit

TCK frequency of operation

0

33.3

MHz

TCK cycle time

30

–

ns

t

JHJL

TCK clock pulse width measured at 1.4V

15

–

ns

TCK rise and fall times

–

2

ns

(2)

TRST assert time

25

–

ns

(3)

Input Setup Times:

Boundary-scan data

TMS, TDI

4

0

–

–

ns

(3)

t

IXJH

Input Hold Times:

Boundary-scan data

TMS, TDI

20

25

–

–

ns

t

JLDV

(4)

Valid Times:

Boundary-scan data

TDO

4

4

20

25

ns

t

JLDX

(4)

Output hold times:

Boundary-scan data

TDO

30

30

–

–

(4)(5)

t

JLOZ

TCK to output high impedance:

Boundary-scan data

TDO

3

3

19

9

ns

Output

Z0 = 50Ω

RL = 50Ω

OVDD/2