WM8772SEDSSLASHRV datasheet(52/73 Pages) WOLFSON

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WM8772EFT – 32 LEAD TQFP

Production Data

PD Rev 4.2 October 2005

DIN1/2/3 are sampled by the WM8772EFT on the rising edge of DACBCLK so the controller must

output DAC data that changes on the falling edge of DACBCLK. ADC data is output on DOUT and

changes on the falling edge of ADCBCLK.

By setting control bit DACBCP the polarity of DACBCLK may be reversed so that DIN1/2/3 are

sampled on the falling edge of DACBCLK.

By setting control bit ADCBCP the polarity of ADCBCLK may be reversed so that DOUT changes on

the rising edge of ADCBCLK.

ADCLRC

DOUT

DACBCLK

DIN1/2/3

DACLRC

WM8772

CODEC

DSP/

ENCODER/

DECODER

ADCBCLK

Figure 46 Master Mode

AUDIO INTERFACE FORMATS

Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio

Interface. 5 popular interface formats are supported:

•

Left Justified mode

•

Right Justified mode

•

2S mode

•

DSP mode A

•

DSP mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the

exception of 32 bit right justified mode, which is not supported.

In left justified, right justified and I

2S modes, the digital audio interface receives DAC data on the

DIN1/2/3 inputs and outputs ADC data on DOUT. Audio Data for each stereo channel is time

multiplexed with ADCLRC or DACLRC indicating whether the left or right channel is present.

ADCLRC or DACLRC is also used as a timing reference to indicate the beginning or end of the data

words.

In left justified, right justified and I

2S modes, the minimum number of DACBCLK/ADCBCLK’s per

DACLRC/ADCLRC period is 2 times the selected word length. ADCLRC/DACLRC must be high for a

minimum of word length DACBCLK/ADCBCLK’s and low for a minimum of word length

DACBCLK/ADCBCLK’s. Any mark to space ratio on ADCLRC/DACLRC is acceptable provided the

above requirements are met.

In DSP mode A or mode B, all 6 DAC channels are time multiplexed onto DIN1. DACLRC is used as

a frame sync signal to identify the MSB of the first word. The minimum number of DACBCLK’s per

DACLRC period is 6 times the selected word length. Any mark to space ratio is acceptable on

DACLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP

mode A or mode B, with ADCLRC used as a frame sync to identify the MSB of the first word. The

minimum number of ADCBCLK’s per ADCLRC period is 2 times the selected word length

WM8772SEDS/RV Datasheet(PDF) 52 Page - Wolfson Microelectronics plc

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