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ADC3683 Datasheet(PDF) 32 Page - Texas Instruments

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No. de pieza ADC3683
Descripción Electrónicos  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3683 Datasheet(HTML) 32 Page - Texas Instruments

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FCLK
Serial LVDS
1-Wire
(18x Serialization)
Serial LVDS
2-Wire
(9x Serialization)
DA1
DA0
DB1
DB0
ChA
ChB
Serial LVDS
1/2-Wire
(36x Serialization)
FCLK
DA0
DB0
FCLK
DA0
B0 <8:0>
A0 <8:0>
B0 <17:9>
A0 <17:9>
DCLK
DCLK
DCLK
B0 <17:0>
A0 <17:0>
B0
D13
B0
D11
B0
D9
B0
D7
B0
D5
B0
D3
B0
D1
B0
D12
B0
D10
B0
D8
B0
D6
B0
D4
B0
D2
B0
D0
B1
D13
B1
D11
B1
D9
B1
D7
B1
D5
B1
D3
B1
D12
B1
D10
B1
D8
B1
D6
B1
D4
B1
D2
B1
D1
B1
D0
A0
D13
A0
D11
A0
D9
A0
D7
A0
D5
A0
D3
A0
D1
A0
D12
A0
D10
A0
D8
A0
D6
A0
D4
A0
D2
A0
D0
A1
D13
A1
D11
A1
D9
A1
D7
A1
D5
A1
D3
A1
D12
A1
D10
A1
D8
A1
D6
A1
D4
A1
D2
A1
D1
A1
D0
B0
D17
B0
D15
B0
D16
B0
D14
A0
D17
A0
D15
A0
D16
A0
D14
B1
D17
B1
D15
B1
D16
B1
D14
A1
D17
A1
D15
A1
D16
A1
D14
Figure 7-35. Output Data Format in Real Decimation (18-bit Output Resolution)
Table 7-5 shows the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of SLVDS lanes (L) and real decimation setting (M).
Table 7-5 shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 18-bit output resolution and
real decimation by 4.
Table 7-5. Serial LVDS Lane Rate Examples with Real Decimation and 18-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DA/B0,1
M
FS
R
L
FS / M / 2 (L = 2)
FS / M (L = 1, 1/2)
[DA/B0,1] / 2
FS x R / L / M
4
65MSPS
18
2
8.125MHz
73.125 MHz
146.25 MHz
1
16.25MHz
146.25 MHz
292.5 MHz
1/2
292.5 MHz
585 MHz
ADC3683-SP
SBASAB5 – MARCH 2024
www.ti.com
32
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: ADC3683-SP



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