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SC515849 Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc |
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SC515849 Datasheet(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 142 page  Device User Guide — 9S12DT128DGV2/D V02.15 61 Freescale Semiconductor Table 2-1 Signal Properties Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Pin Name Function 4 Pin Name Function 5 Powered by Internal Pull Resistor Description CTRL Reset State EXTAL — — — — VDDPLL NA NA Oscillator Pins XTAL — — — — VDDPLL NA NA RESET — — — — VDDR None None External Reset TEST — — — — N.A. None None Test Input VREGEN — — — — VDDX NA NA Voltage Regulator Enable Input XFC — — — — VDDPLL NA NA PLL Loop Filter BKGD TAGHI MODC — — VDDR Always Up Up Background Debug, Tag High, Mode Input PAD[15] AN1[7] ETRIG1 — — VDDA None None Port AD Input, Analog Inputs, External Trigger Input (ATD1) PAD[14:8] AN1[6:0] — — — VDDA None None Port AD Input, Analog Inputs (ATD1) PAD[7] AN0[7] ETRIG0 — — VDDA None None Port AD Input, Analog Inputs, External Trigger Input (ATD0) PAD[6:0] AN0[6:0] — — — VDDA None None Port AD Input, Analog Inputs (ATD0) PA[7:0] ADDR[15:8]/ DATA[15:8] — — — VDDR PUCR/ PUPAE Disabled Port A I/O, Multiplexed Address/Data PB[7:0] ADDR[7:0]/ DATA[7:0] — — — VDDR PUCR/ PUPBE Disabled Port B I/O, Multiplexed Address/Data PE7 NOACC XCLKS — — VDDR PUCR/ PUPEE Mode depen- dant1 Port E I/O, Access, Clock Select PE6 IPIPE1 MODB — — VDDR While RESET pin low: Down Port E I/O, Pipe Status, Mode Input PE5 IPIPE0 MODA — — VDDR Port E I/O, Pipe Status, Mode Input PE4 ECLK — — — VDDR PUCR/ PUPEE Mode depen- dant1 Port E I/O, Bus Clock Output PE3 LSTRB TAGLO — — VDDR Port E I/O, Byte Strobe, Tag Low PE2 R/W — — — VDDR Port E I/O, R/W in expanded modes PE1 IRQ — — — VDDR Up Port E Input, Maskable Interrupt PE0 XIRQ — — — VDDR Port E Input, Non Maskable Interrupt PH7 KWH7 --- — — VDDR PERH/ PPSH Disabled Port H I/O, Interrupt |
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