ADN8102ACPZ-R7 datasheet(29/36 Pages) AD

29 / 36 page

ADN8102

Rev. C | Page 29 of 36

PRINTED CIRCUIT BOARD (PCB) LAYOUT

GUIDELINES

The high speed differential inputs and outputs should be routed

with 100 Ω controlled impedance, differential transmission

lines. The transmission lines, either microstrip or stripline,

should be referenced to a solid low impedance reference plane.

An example of a PCB cross-section is shown in Figure 45. The

trace width (W), differential spacing (S), height above reference

plane (H), and dielectric constant of the PCB material determine

the characteristic impedance. Adjacent channels should be kept

apart by a distance greater than 3 W to minimize crosstalk.

PCB DIELECTRIC

SIGNAL (MICROSTRIP)

SOLDERMASK

PCB DIELECTRIC

REFERENCE PLANE

SIGNAL (STRIPLINE)

Figure 45. Example of a PCB Cross-Section

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended.

The VEE pins should be soldered directly to the ground plane

to reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance. The exposed pad should be connected to the VEE

plane using plugged vias so that solder does not leak through

the vias during reflow.

Use of a 10 μF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

printed circuit board (PCB). It is recommended that 0.1 μF and

1 nF ceramic chip capacitors be placed in parallel at each supply

pin for high frequency, power supply decoupling. When using

0.1 μF and 1 nF ceramic chip capacitors, they should be placed

between the IC power supply pins (VCC, VTTI, and VTTO)

and VEE, as close as possible to the supply pins.

By using adjacent power supply and GND planes, excellent high

frequency decoupling can be realized by using close spacing

between the planes. This capacitance is given by

CPLANE = 0.88εr × A/d (pF)

where:

εr is the dielectric constant of the PCB material.

A is the area of the overlap of power and GND planes (cm2).

d is the separation between planes (mm).

For FR4, εr = 4.4 and 0.25 mm spacing, C ≈ 15 pF/cm2.

Supply Sequencing

Ideally, all power supplies should be brought up to the appropri-

ate levels simultaneously (power supply requirements are set by

the supply limits in Table 1 and the absolute maximum ratings

listed in Table 3). In the event that the power supplies to the

ADN8102 are brought up separately, the supply power-up

sequence is as follows: DVCC is powered first, followed by VCC,

and lastly VTTI and VTTO. The power-down sequence is reversed,

with VTTI and VTTO being powered off first.

VTTI and VTTO contain ESD protection diodes to the VCC power

domain (see Figure 39 and Figure 41). To avoid a sustained high

current condition in these devices (ISUSTAINED < 64 mA), the VTTI

and VTTO supplies should be powered on after VCC and should

be powered off before VCC.

If the system power supplies have a high impedance in the

powered off state, then supply sequencing is not required

provided the following limits are observed:



Peak current from VTTI or VTTO to VCC < 200 mA.



Sustained current from VTTI or VTTO to VCC < 64 mA.

Thermal Paddle Design

The LFCSP is designed with an exposed thermal paddle to

conduct heat away from the package and into the PCB. By

incorporating thermal vias into the PCB thermal paddle,

heat is dissipated more effectively into the inner metal layers

of the PCB. To ensure device performance at elevated

temperatures, it is important to have a sufficient number of

thermal vias incorporated into the design. An insufficient

number of thermal vias results in a θJA value larger than

specified in Table 1. Additional PCB footprint and assembly

guidelines are described in the AN-772 Application Note, A

Design and Manufacturing Guide for the Lead Frame Chip Scale

Package (LFCSP).

It is recommended that a via array of 4 × 4 or 5 × 5 with a

diameter of 0.3 mm to 0.33 mm be used to set a pitch between

1.0 mm and 1.2 mm. A representative of these arrays is shown in

Figure 46.

THERMAL

VIA

THERMAL

PADDLE

Figure 46. PCB Thermal Paddle and Via

ADN8102ACPZ-R7 Datasheet(PDF) 29 Page - Analog Devices

ADN8102ACPZ-R7 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Descarga

Enlace URL