ADN8102ACPZ-R7 datasheet(16/36 Pages) AD

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ADN8102

Rev. C | Page 16 of 36

THEORY OF OPERATION

INTRODUCTION

The ADN8102 is a quad, bidirectional cable and backplane

equalizer that provides both input equalization and output pre-

emphasis on both the line card and cable sides of the device.

The device supports full loopback and through connectivity

of the two unidirectional half-links, each consisting of four

differential signal pairs.

The ADN8102 offers extensively programmable output levels

and pre-emphasis as well as the ability to disable the output

current. The receivers integrate a programmable, multizero

equalizer transfer function that is optimized to compensate

either typical backplane or typical cable losses.

The I/O on-chip termination resistors are terminated to user-

settable supplies to support dc coupling in a wide range of logic

styles. The ADN8102 supports a wide core supply range; VCC

can be set from 1.8 V to 3.3 V. These features, together with

programmable output levels, allow for a wide range of dc- and

ac-coupled I/O configurations.

The ADN8102 supports several control and configuration

modes, as shown in Table 5. The pin control mode offers access

to a subset of the total feature list but allows for a much

simplified control scheme. The primary advantage of using the

serial control interface is that it allows finer resolution in setting

receive equalization, transmitter preemphasis, loss-of-signal

(LOS) behavior, and output levels.

By default, the ADN8102 starts in pin control mode. Strobing

the RESET pin sets all on-chip registers to their default values

and uses pins to configure loopback, PE, and EQ levels. In

mixed mode, loopback is still controlled through the external

pin. The user can override PE and EQ settings in mixed mode.

In serial mode, all functions are accessed through registers, and

the control pin inputs are ignored, except RESET .

The ADN8102 register set is controlled through a 2-wire, I2C

interface. The ADN8102 acts only as an I2C slave device. The 7-bit

slave address for the ADN8102 I2C interface contains the static

value b10010 for the upper four bits. The lower two bits are

controlled by the input pins, ADDR[1:0]

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

TRANSMIT

PRE-EMPHASIS

RECEIVE

EQUALIZATION

2:1

CONTROL LOGIC

ADN8102

Ix_B[3:0]

LOS_B

Ox_A[3:0]

ADDR[1:0]

SCL

SDA

RESET

Ox_B[3:0]

LOS_A

Ix_A[3:0]

PE_A[1:0]

EQ_A[1:0]

EQ_B[1:0]

PE_B[1:0]

ENA

ENB

Figure 38. Simplified Functional Block Diagram

Table 5. Control Interface Mode Register

Address

Default

Bit

Bit Name

Functionality Description

0x0F

0x00

Control

7:2

Reserved

Set to 0.

interface mode

1:0

MODE[1:0]

00 = toggle pin control. Asynchronous control through toggle pins only.

01 = Loopback control via toggle pins, equalization, and preemphasis via

10 = Equalization and preemphasis via toggle pins and loopback control

via register-based control through the I2C serial interface.

11 = serial control. Register-based control through the I2C serial interface.

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