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ADN8102ACPZ-R7 Datasheet(PDF) 20 Page - Analog Devices |
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ADN8102ACPZ-R7 Datasheet(HTML) 20 Page - Analog Devices |
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20 / 36 page  ADN8102 Rev. C | Page 20 of 36 LOOPBACK The ADN8102 provides loopback on both input ports (Port A: cable interface input, and Port B: line card interface input). The external loopback toggle pin, LB, controls the loopback of the Port B input only (board side loopback). When loopback is asserted, valid data continues to pass through the Port B link, but the Port B input signals are also shunted to the Port A output to allow testing and debugging without disrupting valid data. This loopback, as well as loopback of the Port A input (cable side loopback), can be programmed through the I2C interface. The loopbacks are controlled through the I2C interface by writing to Bit 0 and Bit 1 of the loopback control register (Register 0x02). Bit 0 represents loopback of the Port A inputs to the Port B outputs (cable side loopback). Bit 1 represents loopback of the Port B inputs to the Port A outputs (board side loopback), with high representing loopback for both bits. Bit 1 can be overridden by the LB pin if the pin mode register is set to enable loopback via external pin as shown in Table 5. Both input ports can be looped back simultaneously (full loopback) by writing high to both Bit 0 and Bit 1, but in this case, valid data is disrupted on each channel. Figure 40 illustrates the three loopback modes. CONTROL LOGIC TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION EQ Ix_B[3:0] LB ADDR[1:0] SCL SDA RESET Ox_B[3:0] LOS_A Ix_A[3:0] PE_A[1:0] EQ_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE PE Ox_A[3:0] CONTROL LOGIC TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION EQ Ix_B[3:0] LB ADDR[1:0] SCL SDA RESET Ox_B[3:0] LOS_A Ix_A[3:0] PE_A[1:0] EQ_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE PE Ox_A[3:0] CONTROL LOGIC TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION EQ Ix_B[3:0] LB ADDR[1:0] SCL SDA RESET Ox_B[3:0] LOS_A Ix_A[3:0] PE_A[1:0] EQ_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE PE Ox_A[3:0] CABLE SIDE LOOPBACK BOARD SIDE LOOPBACK FULL LOOPBACK Figure 40. Loopback Modes of Operation Table 12. Loopback Control Functionality Control Mode1 LB Pin LB[1] LB[0] Description Pin Control (00 or 01) 0 X2 X Loopback disabled 1 X X Board side loopback enabled Serial Control X 0 0 Loopback disabled (10 or 11) X 0 1 Cable side loopback enabled X 1 0 Board side loopback enabled X 1 1 Full loopback enabled 1 Refer to Table 5 for additional information regarding control mode settings. 2 X = don’t care. Table 13. Loopback Control Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Loopback control 0x02 LB[1] LB[0] 0x00 |
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