TMP93CS41 datasheet(48/248 Pages) TOSHIBA

48 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-46

* Clock condition

System clock: fc

Clock gear:

1 (fc)

When the hardware configuration is as follows:

DRAM mapping size:

= 1 Mbyte

DRAM data bus size:

= 8 bits

DRAM mapping address range:

= 100000H to 1FFFFFH

Set the following registers first; refresh is performed automatically.

1. Register initial value setting

XIX, 100000H

LDC

DMAS0, XIX

... Mapping start address

00001010B

LDC

DMAM0, A

... Read only mode (for DRAM refresh)

2. Timer setting

Set the timers so that interrupts are generated at intervals of 62.5

µs or less.

3. Interrupt controller setting

Set the timer interrupt mask higher than the mask for other interrupts. Write the

above timer interrupt vector value into the micro DMA start vector register, DMA0V.

(Operation description)

The DRAM data bus is an 8-bit bus and the micro DMA is in read-only mode (4 bytes),

so refresh is performed four times per interrupt.

When a 512-refresh per 8 ms DRAM is connected, DRAM refresh is performed

sufficiently if the micro DMA is started every 15.625

µs × 4 = 62.5 µs or less, since the

timing is 15.625

µs per refresh.

(Overhead)

Each processing time for read-only mode by the micro DMA is 1.8

µs (18 states) at 20

MHz with an 8-bit data bus.

In the above example, the micro DMA is started every 62.5

µs, and 1.8 µs ÷ 62.5 µs =

0.0288; thus, the overhead factor is 2.88%.

Note:

When the bus which must wait to accept the interrupt is released ( BUSAK

= “0”),

DRAM refresh is not performed because the micro DMA is generated by an

interrupt.

TMP93CS41 Datasheet(PDF) 48 Page - Toshiba Semiconductor

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