TMP93CS41 datasheet(56/248 Pages) TOSHIBA

56 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-54

Table 3.5.2 I/O Registers and Specifications (1/2)

I/O Register

Port No.

Pin No.

Function

PnCR

PnFC

Input port (Note 1)

Output port (Note 1)

Port 0

P00 to P07

AD0 to AD7 bus

None

Input port (Note 1)

Output port (Note 1)

AD8 to AD15 bus (Note 2)

Port 1

P10 to P17

A8 to A15 output (Note 2)

Input port (without PD)

Input port (with PD)

Output port

A0 to A7 output (Note 1)

Port 2

P20 to P27

A16 to A23 output

Output port (Note 1)

Outputs RD only when accessing external space

P30

Always outputs RD

None

Output port (Note 1)

P31

Outputs WR only when accessing external space

None

Input port (without PU)

Input port (with PU)

P32 to P37

Output port

P32

HWR

output

WAIT

input (without PU)

P33

WAIT

input (with PU)

None

BUSRQ

input (without PU)

P34

BUSRQ

input (with PU)

P35

BUSAK

output

P36

output

Port 3

P37

RAS

output

Input port (without PU)

Input port (with PU)

P40 to P41

Output port

Input port (without PD)

Input port (with PD)

P42

Output port

P40

CS0

output (Note 3)

P41

CS1

output (Note 3)

Port 4

P42

CS2

output (Note 3)

Input port

Port 5

P50 to P57

AN0 to AN7 input (Note 4)

None

Input port (without PU)

Input port (with PU)

Output port

Port 6

P60 to P67

PGn output

×: Don’t care

Note 1: In the case of the TMP93CS41F, this function is not available.

Note 2: In the case of the TMP93CS41F, this function is fixed by AM8/ AM16 pin.

Note 3: CS/WAIT control register BnCH<BnCAS> selects the wave form output from P40 to P42 pins, CS0 to CS2 or

CAS

Note 4: The channel for AD input is selected by ADMOD2<ADCHn> for P50 to P57 pins.

Note 5: PU

= pull-up resistor; PD = pull-down resistor.

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