TMP93CS41 datasheet(102/248 Pages) TOSHIBA

102 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-100

3. Timer registers

These are 8-bit registers for setting a time interval. When the values of the timer

registers match the values of the corresponding up counters, the comparator match detect

signal becomes active. If the set value is 00H, this signal becomes active when the up

counter overflows.

Timer register TREG0 has a double buffer.

The timer flip-flop control register TFFCR<DBEN> bit controls whether the double

buffer structure should be enabled or disabled. It is disabled when <DBEN>

= “0” and

enabled when it is set to “1”.

In the double buffer enable state, the data set in the register buffer are transferred to the

timer register when the 2n

− 1 overflow occurs in PWM mode, or at the PPG cycle in PPG

mode. Therefore, during timer mode, the double buffer cannot be used.

Upon resetting, TFFCR will be initialized to <DBEN>

= “0”, disabling the double buffer.

To use the double buffer, write data in the timer register, set <DBEN> to “1”, and write the

following data in the register buffer.

Figure 3.7.3 Configuration of Timer Register 0

Note:

The timer register and the register buffer are allocated at the same memory address.

When <DBEN> = 0, the same value is written in the register buffer and in the timer

The memory address of each timer register is as follows.

TREG0: 000022H

TREG1: 000023H

Both of these registers are write-only and cannot be read.

Up counter

Comparator (CP0)

Timer register 0 (TREG0)

Internal data bus

Write

Selector

TFFCR<DBEN>

Matching detection of PPG

cycle

− 1 overflow of PWM

TREG0 WR

Shift trigger

TMP93CS41 Datasheet(PDF) 102 Page - Toshiba Semiconductor