STM32H523VCU6 datasheet(42/228 Pages) STMICROELECTRONICS

42 / 228 page

Functional overview

STM32H523xx

42/228

DS14540 Rev 1

3.29

HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm

(SHA-1, SHA-224, SHA-256, SHA-512) and the HMAC (keyed-hash message

authentication code) algorithm. HMAC is suitable for applications requiring message

authentication.

The HASH computes FIPS (Federal information processing standards) approved digests of

length of 160, 224, 256, 512 bits, for messages of up to (264 – 1).

The HASH main features are:

•

Suitable for data authentication applications, compliant with:

–

Federal Information Processing Standards Publication FIPS PUB 180-4, Secure

Hash Standard (SHA-1 and SHA-2 family)

–

Federal Information Processing Standards Publication FIPS PUB 186-4, Digital

Signature Standard (DSS)

–

Internet Engineering Task Force (IETF) Request For Comments RFC 2104,

HMAC: Keyed-Hashing for Message Authentication and Federal Information

Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message

Authentication Code (HMAC)

•

Fast computation of SHA-1, SHA-224, SHA-256 and SHA-512

–

82 (respectively 66) clock cycles for processing one 512-bit block of data using

SHA-1 (respectively SHA-256) algorithm

•

Corresponding 32-bit words of the digest from consecutive message blocks are added

to each other to form the digest of the whole message

–

Automatic 32-bit words swapping to comply with the internal little-endian

representation of the input bit string

–

Word swapping supported: bits, bytes, half-words and 32-bit words

•

Automatic padding to complete the input bit string to fit digest minimum block size of

512 bits (16 × 32 bits)

•

Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,

corresponding to one block size

•

AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB

error is generated)

•

8 × 32-bit words (H0 to H7) for output message digest

•

Automatic data flow control with support of direct memory access (DMA) using one

channel. Single or fixed burst of 4 supported.

•

Interruptible message digest computation, on a per-32-bit word basis

–

Re-loadable digest registers

–

Hashing computation suspend/resume mechanism, including using DMA

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