7.2.2.2 Input Filter Design

Place a differential RC filter (R1, R2, C5) in front of the isolated modulator to improve signal-to-noise

performance of the signal path. Input noise with a frequency close to the ΔΣ modulator sampling frequency

(typically 20MHz) is folded back into the low-frequency range by the modulator. The purpose of the RC filter

at the input is to attenuate high-frequency noise below the desired noise level of the measurement. Design the

input filter such that:

• The filter capacitance (C5) is a minimum of 10nF

• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (fCLKIN)

of the ΔΣ modulator

• The dynamic input bias current does not generate significant voltage drop across the DC impedances (R1,

R2) of the input filter

• The impedances measured from the analog inputs are equal (R1 equals R2)

Capacitors C6 and C7 are optional and improve common-mode rejection at high frequencies (>1MHz). For

best performance, make sure C6 matches the value of C7 and that both capacitors are 10 to 20 times

lower in value than C5. NP0-type capacitors offer low temperature drift and low voltage coefficients, and are

preferred for common-mode filtering. For most applications, the structure shown in Figure 7-2 achieves excellent

performance.

R2

10

R1 10

C5

10 nF

AVDD

AGND

INP

INN

DVDD

CLKIN

DOUT

DGND

C6

1 nF

C7

1 nF

Figure 7-2. Input Filter

7.2.2.3 Bitstream Filtering

The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a

conversion result of a conventional analog-to-digital converter (ADC). Equation 2 shows a sinc3-type filter, which

is a very simple filter built with minimal effort and hardware.

3

OSR

1

1

z

H z

1

z

§

·

¨

¸

¨

¸

©

¹

(2)

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a

second-order modulator. All characterization in this document is done with a sinc3 filter with an oversampling

ratio (OSR) of 256 and a 16-bit output word width.

The Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications

application note discusses an example code. Use this example code for implementing a sinc3 filter in an FPGA.

This application note is available for download at www.ti.com.

For modulator output bitstream filtering, use a device from TI's C2000 or Sitara microcontroller families. These

families support multichannel dedicated hardwired filter structures that significantly simplify system level design

by offering two filtering paths per channel. One path provides high-accuracy results for the control loop and the

other provides a fast-response path for overcurrent detection.

A delta sigma modulator filter calculator is available for download at www.ti.com that aids in filter design and

correct OSR and filter order selection. This calculator helps achieve the desired output resolution and filter

response time.

AMC0106M05

SBASAS7A – AUGUST 2024 – REVISED JUNE 2025

www.ti.com

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