STA680 datasheet(47/48 Pages) STMICROELECTRONICS

47 / 48 page

DS5877 Rev 13

47/48

STA680

Revision history

14-Apr-2016

Updated document Title.

Added: “AEC-Q100 qualified” as first Features in cover page.

Removed LQFP144 package image and ‘STA680Q’ Order code

inTable 1: Device summary.

Updated: Section 1.2: Ball-out description; Figure 4: System block

diagrams on page 20; Section 2.1: Receiver system overview;

Section 2.2: HD Radio processing; Section 3.1: Clock schemes;

Section 3.2: Power on; Section 4: Power supply ramp-up phase;

Section 5.1: Interfaces: LFBGA vs. TFBGA; Section 5.2: Base-band

I2S interface; Section 5.3: Base-band I2S interface frequency

diversity; Section 5.4.1: Output serial audio interface (SAI);

Section 5.5.2: Flash serial peripheral interface (SPI2); Section 5.6:

I2C interfaces; Section 5.7: SDRAM interface; Section 6.1: Absolute

maximum ratings; Section 6.2: Thermal data. Section 6.3: Operating

conditions; and Section 7: Package information.

17-Mar-2017

Updated:

– Features and Description in cover page;

– Table 2: Ball-out description;

– Section 4.2: Boot sequence;

– Table 6: Baseband interfaces pin list;

– Table 8: AIF pin list;

– Section 5.4.1: Output serial audio interface (SAI);

– Added paragraph title Section 5.4.2: Input serial audio interface;

– Section 5.4.3: Audio sample rate converter (ASRC)

– Section 5.5: Serial peripheral interfaces (SPI);

– Table 11: Host micro SPI pin list;

– Table 12: Flash SPI pin list;

– Section 5.7: SDRAM interface.

22-Mar-2019

Updated:

– Table 18: Absolute maximum rating on page 38;

– Table 20: DC electrical characteristics on page 39.

Table 23. Document revision history (continued)

Date

Revision

Changes

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