Pin Definitions

Name

Pin #

Description

DI, DI

8, 9

Differential data inputs.

DO, DO

13,

14

Differential collector data

outputs (ECL compatible).

AEC+,

AEC−

6, 7

AEC loop filter pins.

A capacitor connected

between these pins governs

the loop response for the

adaptive equalization loop.

OEM

3

Eye monitor output. The

output of the equalization

filter.

CD

5

Carrier detect. (Low when no

signal is present).

MUTE

12

Output MUTE. (Active low.)

Carrier detect may be tied to

this pin to inhibit the output

when no signal is present.

V

CC

1, 2,

4

Positive supply pins (ground

or +5V).

V

EE

10, 11 Negative supply pins (−5.2V

or ground).

Operation

The CLC014 Adaptive Cable Equalizer provides a complete

solution for equalizing high-bit-rate digital data transmitted

over long transmission lines. The following sections furnish

design and application information to assist in completing a

successful design:

•

Block diagram explanation of the CLC014

•

Recommended standard input and output interface con-

nections

•

Common applications for the CLC014

•

Measurement, PC layout, and cable emulation boxes

For applications assistance in the U.S., call 800-272-9959 to

contact a technical staff member.

BLOCK DESCRIPTION

The CLC014 is an adaptive equalizer that reconstructs serial

digital data received from transmission lines such as coaxial

cable or twisted pair. Its transfer function approximates the

reciprocal of the cable loss characteristic. The block diagram

in Figure 2 depicts the main signal conditioning blocks for

equalizing digital data at the receiving end of a cable. The

CLC014 receives baseband differential or single-ended digi-

tal signals at its inputs DI and DI.

The Equalizer block is a two-stage adaptive filter. This filter

is capable of equalizing cable lengths from zero meters to

lengths that require 40 dB of boost at 200 MHz.

The Quantized Feedback Comparator block receives the

differential signals from the equalizer filter block. This block

includes two comparators. The first comparator incorporates

a self-biasing DC restore circuit. This is followed by a second

high-speed comparator with output mute capability. The sec-

ond comparator receives and slices the DC-restored data.

Its outputs DO and DO are taken from the collectors of the

output transistors. MUTE latches DO and DO when a TTL

logic low level is applied.

The Adaptive Servo Control block produces the signal for

controlling the filter block, and outputs a voltage proportional

to cable length. It receives differential signals from the output

of the filter block and from the quantized-feedback compara-

tor (QFBC) to develop the control signal. The servo loop

response is controlled by an external capacitor placed

across the AEC+ and AEC− pins. Its output voltage, as

measured differentially across AEC+ and AEC−, is roughly

proportional to the length of the transmission line. For

Belden 8281 coaxial cable this differential voltage is about

1.5 mV/meter. Once this voltage exceeds 500 mV, no addi-

tional equalization is provided.

The Carrier Detect (CD) block monitors the signal power out

of the equalizing filter and compares it to an internal refer-

ence to determine if a valid signal is present. A CMOS high

output indicates that data is present. The output of CD can

be connected to the MUTE input to automatically latch the

outputs (DO and DO), preventing random transitions when

no data is present.

The Output Eye Monitor (OEM) provides a single-ended

buffered output for observing the equalized eye pattern. The

OEM output is a low impedance high-speed voltage driver

capable of driving an AC-coupled 100

Ω load.

10005620

FIGURE 1. CLC014 Equalizer Application Circuit

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