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3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002
Page 4 of 9
Z9952
AC Parameters
1
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
Freq
Reference Input Frequency
Note 2
Note 2
MHz
Fvco
PLL VCO Lock Range
200
480
MHz
Tlock
Maximum PLL lock Time
10
ms
Tr / Tf
Output Clocks Rise / Fall Time
4,5
0.10
1.0
ns
0.8V to 2.0V
-
180
QB, QC = (
÷2)
120
QA, QB, QC = (
÷4)
Fout
Maximum Output Frequency
80
MHz
QA = (
÷6)
FoutDC
Output Duty Cycle
4,5
TCYCLE/2 –
750
TCYCLE/2 +
750
ps
tpZL, tpZH
Output enable time (all outputs)
2
10
ns
tpLZ, tpHZ
Output disable time (all outputs)
2
8
ns
TCCJ
Cycle to Cycle Jitter (peak to peak)
5
+/- 100
ps
Tpd
REFCLK to FB_IN Delay
3,,4,5
-200
200
ps
-
150
Same frequencies
TSKEW0
Any Output to Any Output Skew
4,5
250
ps
Different frequencies
VDDA = VDD = VDDC = 3.3V +/- 5%, TA = -40
°°°°C to +85°°°°C
Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with
loaded outputs.
Note 2: Maximum and minimum input reference is limited by the VCO lock range.
Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the
minimum limits with an increase/decrease of the input reference clock period.
Note 4: Driving series or parallel terminator 50
Ω (or 50Ω to VDD/2).
Note 5: Outputs loaded with 30pF each
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