3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002
Page 3 of 9
Z9952
Maximum Ratings¹
Maximum Input Voltage Relative to VSS:
VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
-65
°C to + 150°C
Operating Temperature:
-40
°C to +85°C
Maximum ESD protection
2KV
Maximum Power Supply:
5.5V
Maximum Input Current:
±20mA
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Input Low Voltage
VIL
VSS
-
0.8
V
Input High Voltage
VIH
2.0
-
VDD
V
Input Low Current (@VIL = VSS)
IIL
10
µA
Input High Current (@VIL =VDD)
IIH
120
µA
Note 2
Output Low Voltage
VOL
0.5
V
IOL = 20mA, Note 3
Output High Voltage
VOH
2.4
V
IOH = -20mA, Note 3
Quiescent Supply Current
IDDC
-
15
20
mA
All VDDC, VDDA, and VDD
PLL Supply Current
IDD
-
15
20
mA
VDDA only
Input Capacitance
Cin
-
-
4
pF
VDDA = VDD = VDDC = 3.3V
±±±±5%, TA = -40°°°°C to +85°°°°C
Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is
NOT required.
Note 2: Inputs have internal pull-down resistors that affect input current.
Note 3: Driving series or parallel terminated 50
Ω (or 50Ω to VDD/2) transmission lines.
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