ST7LITE1XB datasheet(28/157 Pages) STMICROELECTRONICS

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ST7LITE1xB

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7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 16:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

Note: A reset can also be triggered following the

detection of an illegal opcode or prebyte code. Re-

fer to section 12.2.1 on page 107 for further de-

tails.

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 15:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (see table

below)

■ RESET vector fetch

Caution: When the ST7 is unprogrammed or fully

erased, the Flash is blank and the RESET vector

is not programmed. For this reason, it is recom-

mended to keep the RESET pin in low state until

programming mode is entered, in order to avoid

unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the

oscillator to stabilise and ensures that recovery

has taken place from the Reset state. The shorter

or longer clock cycle delay is automatically select-

ed depending on the clock source chosen by op-

tion byte:

The RESET vector fetch phase duration is 2 clock

cycles.

If the PLL is enabled by option byte, it outputs the

clock after an additional delay of tSTARTUP (see

Figure 13).

Figure 15. RESET Sequence Phases

7.5.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain

output with integrated RON weak pull-up resistor.

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

Electrical Characteristic section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in

order to be recognized (see Figure 17). This de-

tection is asynchronous and therefore the MCU

can enter reset state even in HALT mode.

Clock Source

CPU clock

cycle delay

Internal RC Oscillator

256

External clock (connected to CLKIN pin)

256

External Crystal/Ceramic Oscillator

(connected to OSC1/OSC2 pins)

4096

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

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