AS7261 datasheet(29/48 Pages) AMSOSRAM

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AS7261 − Detailed Descriptions

UART Interface

If selected by the I2C_ENB pin setting, the UART module

implements the TX and RX signals as defined in the RS-232 /

V.24 standard communication protocol.

It has on both, receive and transmit path, a 16 entry deep FIFO.

It can generate interrupts as required.

UART Feature List1

• Full Duplex Operation (Independent Serial Receive and

Transmit Registers) with FIFO buffer of 8 byte for each.

• At a clock rate of 16MHz it supports communication at

115200 Baud.

• Supports Serial Frames with 8 Data Bits, no Parity and 1

Stop Bit

Theory of Operation

TRANSMISSION

If data is available in the transmit FIFO, it will be moved into the

output shift register and the data will be transmitted at the

configured Baud Rate, starting with a Start Bit (logic zero) and

followed by a Stop Bit (logic one).

RECEPTION

At any time, with the receiver being idle, if a falling edge of a

start bit is detected on the input, a byte will be received and

stored in the receive FIFO. The following Stop Bit will be checked

to be logic one.

Addr: 0x20:0x23

Cal_DUV

Bit

Bit Name

Default

Access

Bit Description

31:0

Cal_DUV

Calibrated DUV (CIE 1976) (4-byte floating-point)

Addr: 0x24:0x27

Cal_LUX

Bit

Bit Name

Default

Access

Bit Description

31:0

Cal_LUX

Calibrated LUX (4-byte)

Addr: 0x28:0x2B

Cal_CCT

Bit

Bit Name

Default

Access

Bit Description

31:0

Cal_CCT

Calibrated CCT (4-byte)

1. With UART operation, min VDD of 2.97V is required as shown in Electrical Characteristics figures.

AS7261 Datasheet(PDF) 29 Page - ams-OSRAM AG

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