PSD813F2 datasheet(78/110 Pages) STMICROELECTRONICS

78 / 110 page

PSD835G2

PSD8XX Family

NOTE: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC.

2. CSI deselected or internal Power Down mode is active.

3. PLD is in non-turbo mode and none of the inputs are switching

4. Refer to Figure 32 for PLD current calculation.

5. IO = 0 mA

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VCC

Supply Voltage

All Speeds

4.5

5.5

VIH

High Level Input Voltage

4.5 V < VCC < 5.5 V

VCC +.5

VIL

Low Level Input Voltage

4.5 V < VCC < 5.5 V

–.5

0.8

VIH1

Reset High Level Input Voltage

(Note 1)

.8 VCC

VCC +.5

VIL1

Reset Low Level Input Voltage

(Note 1)

–.5

.2 VCC –.1

VHYS

Reset Pin Hysteresis

0.3

VLKO

VCC Min for Flash Erase and Program

2.5

4.2

VOL

Output Low Voltage

IOL = 20 µA, VCC = 4.5 V

0.01

0.1

IOL = 8 mA, VCC = 4.5 V

0.25

0.45

VOH

Output High Voltage Except VSTBY On

IOH = –20 µA, VCC = 4.5 V

4.4

4.49

IOH = –2 mA, VCC = 4.5 V

2.4

3.9

VOH

Output High Voltage VSTBY On

IOH

= –1 µA

VSBY – 0.8

VSBY

SRAM Standby Voltage

2.0

VCC

ISBY

SRAM Standby Current (VSTBY Pin)

VCC = 0 V

0.5

µA

IIDLE

Idle Current (VSTBY Pin)

VCC > VSBY

–0.1

0.1

µA

VDF

SRAM Data Retention Voltage

Only on VSTBY

ISB

Standby Supply Current for Power

CSI > VCC –0.3 V

100

200

µA

Down Mode

(Notes 2, 3 and 5)

ILI

Input Leakage Current

VSS < VIN < VCC

–1

±.1

µA

ILO

Output Leakage Current

0.45 < VIN < VCC

–10

±5

µA

Output Current

Refer to IOL and IOH in

the VOL and VOH row

PLD_TURBO = OFF,

0mA

f = 0 MHz (Note 3)

PLD Only

PLD_TURBO = ON,

f = 0 MHz

400

700

µA/PT

ICC (DC)

Operating Supply

During Flash Write/Erase

(Note 5)

Current

Flash

Only

Read Only, f = 0 MHz

SRAM

f = 0 MHz

PLD AC Base

Fig. 32

ICC (AC)

(Note 4)

(Note 5)

FLASH AC Adder

2.5

3.5

mA/MHz

SRAM AC Adder

1.5

3.0

mA/MHz

PSD835G2 DC Characteristics (5 V ± 10% Versions)

PSD813F2 Datasheet(PDF) 78 Page - STMicroelectronics

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