PSD813F2 datasheet(12/110 Pages) STMICROELECTRONICS

12 / 110 page

PSD835G2

PSD8XX Family

Table 6 shows the offset addresses to the PSD835G2 registers relative to the CSIOP base

address. The CSIOP space is the 256 bytes of address that is allocated by the user to the

internal PSD835G2 registers. Table 6 provides brief descriptions of the registers in CSIOP

space. For a more detailed description, refer to section 9.

7.0 PSD835G2

Description and

Address Offset

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Other*

Description

Data In

Reads Port pin as input,

MCU I/O input mode

Control

Selects mode between

MCU I/O or Address Out

Stores data for output

Data Out

to Port pins, MCU I/O

output mode

Direction

Configures Port pin as

input or output

Configures Port pins as

either CMOS or Open

Drive Select

Drain on some pins, while

selecting high slew rate

on other pins.

Input Micro

⇔Cell

Reads Input Micro

⇔Cells

Reads the status of the

Enable Out

output enable to the I/O

Port driver

Read – reads output of

Output

Micro

⇔Cells A

Micro

⇔Cells A

Write – loads Micro

⇔cell

Flip-Flops

Read – reads output of

Output

Micro

⇔Cells B

Micro

⇔Cells B

Write – loads Micro

⇔cell

Flip-Flops

Mask

Blocks writing to the

Micro

⇔Cells A

Output Micro

⇔Cells A

Mask

Blocks writing to the

Micro

⇔Cells B

Output Micro

⇔Cells B

Flash Protection

Read only – Flash Sector

Protection

Flash Boot

Read only – PSD Security

Protection

and Flash Boot Sector

Protection

JTAG Enable

Enables JTAG Port

PMMR0

Power Management

PMMR2

Power Management

Page

Page Register

Places PSD memory

areas in Program and/or

Data space on an

individual basis.

Memory_ID0

Read only – Flash and

SRAM size

Memory_ID1

Read only – Boot type

and size

Table 6. Register Address Offset

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