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PSD813F2 Datasheet(PDF) 88 Page - STMicroelectronics |
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PSD813F2 Datasheet(HTML) 88 Page - STMicroelectronics |
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88 / 110 page  PSD835G2 PSD8XX Family 87 PSD835G2 AC/DC Parameters – CPLD Timing Parameters (3.0 V to 3.6 V Versions) -90 -12 Slew PT TURBO Rate Symbol Parameter Conditions Min Max Min Max Aloc OFF (Note 1) Unit GPLD Input Pin/Feedback to tPD GPLD Combinatorial Output 38 43 Add 4 Add 20 Sub 6 ns tEA GPLD Input to GPLD Output Enable 43 45 Add 20 Sub 6 ns tER GPLD Input to GPLD Output Disable 43 45 Add 20 Sub 6 ns tARP GPLD Register Clear or Preset Delay 38 43 Add 20 Sub 6 ns tARPW GPLD Register Clear or 28 30 Add 20 ns Preset Pulse Width tARD GPLD Array Delay Any Micro ⇔Cell 23 27 Add 4 ns GPLD Combinatorial Timing (3.0 V to 3.6 V Versions) -90 -12 Slew PT TURBO Rate Symbol Parameter Conditions Min Max Min Max Aloc OFF (Note 1) Unit Maximum Frequency External Feedback 1/(tS +t CO) 24.3 20.4 MHz Maximum Frequency fMAX Internal Feedback ( fCNT) 1/(tS +t CO–10) 32.2 25.6 MHz Maximum Frequency Pipelined Data 1/(tCH +t CL) 45.0 35.7 MHz tS Input Setup Time 18 23 Add 4 Add 20 ns tH Input Hold Time 0 0 ns tCH Clock High Time Clock Input 11 14 ns tCL Clock Low Time Clock Input 11 14 ns tCO Clock to Output Delay Clock Input 23 26 Sub 6 ns tARD GPLD Array Delay Any Micro ⇔Cell 23 27 Add 4 ns tMIN Minimum Clock Period tCH +t CL(Note 2) 22 28 ns GPLD Micro ⇔Cell Synchronous Clock Mode Timing (3.0 V to 3.6 V Versions) NOTES: 1. Fast Slew Rate output available on Port C and F. 2. CLKIN tCLCL = tCH + tCL. NOTE: 1. Fast Slew Rate output available on Port C and F. |
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