TDA7572 datasheet(42/64 Pages) STMICROELECTRONICS

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Modulator

TDA7572

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Pulse injection is being used with the clocked PWM scheme to prevent missing pulses from

an over-modulation condition. The minimum pulse width is dynamically determined by

looking at the delay from the comparator output to the actual switching of the FET stage.

This delay is used to extend any pulses from the modulator that would otherwise be too

short. Circuitry is provided to keep the integrator hovering near the level at which limiting

first occurred, which prevents transients once we leave the over modulation condition. This

is done by summing in a current that is proportional to the amount of time that the pulse is

extended.

Since only three- state modulation is supported, it may prove necessary to slightly delay the

clock going to one modulator to prevent the noise from the switching of one modulator

affecting the second modulator when there is no audio input. This can be done with a small

RC on the clock feeding one modulator. The same result could be obtained adding the RC

on the feedback feeding one modulator.

The reference voltage of the modulator changes from SVR at it's input, to Vcc/2 at its output.

This allows output signal to be centered between the supply rails, increasing unclipped

output voltage swing by preventing asymmetric clipping. This is accomplished using the

LVLSFT pin, as described in the previous paragraph. It has been pointed out that there is

potential for abrupt transients at the output stage, as this scheme will attempt to have the

outputs track VCC/2, while it may be better for avoiding pops to have them rise slowly with

SVR. The end user needs to make this decision by making or not the connection between

HVCC and LVLSFT pin. Will not be present pop noise in a system with perfect symmetry

between the two modulators branch. Pop noise will rise with increasing of asymmetry.

7.1

FET drive

Gate drive circuits are provided to drive complementary external FETS. An internal regulator

to supply the low side gate drivers provides a voltage 10V above VSM. This fully enhances

the FETs without exceeding their VGS limits. A separate regulator 10V below VSP, is used

for the high side gate drivers.

Shoot-through is prevented by sensing VGS of each FET with a dedicated sense line

(GateSensing), and blocking the opposite FET turn-on if the active FET in a ½ bridge has a

|VGS|> |VThreshold|. This allows discrete components to be used to adjust gate charging

without concern over shoot-through.

The drivers are capable to provide high current for a short time (about 5µs) and a lower

current after this time(~150mA). This is done to give enough charge current at the

commutation and avoid short-cut overcurrent.

The VDS of the enhanced FET of each ½ bridge is used monitor current and detect

overcurrent condition. The sensed VDS signal is blanked such that sensing is only active

when the FET is enhanced and any turn on transients have settled. There are two type of

overcurrent intervention: current limitation, cycle-by-cycle limitation. The current limitation

Table 32.

PWMClock table

PWMClock [1:0]

Ratio

Nominal frequency

FNOM/2

55KHz

FNOM

110KHz

FNOM*2

220KHz

FNOM

110KHz

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