ADATE320 datasheet(61/78 Pages) AD

61 / 78 page

Data Sheet

ADATE320

APPLICATIONS INFORMATION

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Rev. C | 61 of 78

POWER SUPPLY, GROUNDING, AND TYPICAL

DECOUPLING STRATEGY

The ADATE320 is internally divided into a digital core and an

analog core.

The VDD and DGND pins provide power and ground for the digital

core that includes the SPI, certain logic functions, and the digital

calibration functions. DGND is the logic ground reference for the

VDD supply. Therefore, bypass VDD adequately to DGND with

good quality, low effective series resistance (ESR) bypass capac-

itors. To reduce transient digital switching noise coupling to the

analog core, connect DGND to a dedicated external ground plane

that is separated from the analog ground domains. If the application

permits, the DGND pins can share a digital ground domain with the

supervisory FPGA or ASIC that interfaces with the ADATE320 SPI.

All CMOS inputs and outputs are referenced between VDD and

DGND, and their valid levels must be guaranteed relative to these

power supply pins.

The analog core of the device includes all analog ATE functional

blocks such as the DACs, the driver, the comparator, the load,

and the PPMU. The VCC and VEE supplies provide power to

the analog core. AGND and PGND are analog ground and power

ground references, respectively. PGND is generally noisier with

analog switching transients, and it may also have large static dc

currents. AGND is generally quieter and has relatively smaller static

dc currents. These two grounds can be connected together outside

the chip to a single shared analog ground plane. Regardless, keep

PGND and AGND (whether separated or shared) separated from

the DGND ground plane if system design constraints permit.

The transient frequencies generated by the analog core can be a

full order of magnitude greater than those generated by the SPI

and on-chip digital circuitry. Therefore, pay close attention to the

decoupling of the VCC and VEE supplies. Each supply must be ad-

equately bypassed to the PGND ground domain using the highest

quality bypass capacitors available. Locate the decoupling capaci-

tors as close to the device as practically possible. The decoupling

capacitors must have very low ESR and effective series inductance

(ESL). Commonly available ceramic capacitors may provide only

a marginally low impedance path to ground at the frequencies

encountered in the ADATE320. Therefore, consider only the highest

performance decoupling capacitors if possible. In accordance with

generally accepted practices, a typical 10 µF tantalum capacitor

must also be shared across each power supply domain.

Pay particularly close attention to decoupling the VCC and VEE

supplies in proximity to the transmission line at the DUTx pins of the

device. To avoid undesired waveform aberrations and degradation

of performance, it is important that all return currents to and from

the transmission line have a direct and low impedance path back to

the VCCDx and VEEDx pins adjacent to the respective DUTx pins.

See Figure 135 for a typical transmission line decoupling strategy.

The ADATE320 has a DUTGND reference input pin that senses the

remote low frequency ground potential at the target device under

test (DUT). With the exception of the VIOH and VIOL active load

currents and VPMU when in PPMU FI mode, all DAC levels are

adjusted on-chip relative to this DUTGND input. Furthermore, the

PPMU measure output pins (PPMU_Mx) are also referenced to

DUTGND. The off-chip system analog-to-digital converter (ADC)

that measures the PPMU_Mx pins must therefore be referenced to

DUTGND as well. Referencing the system ADC to AGND results

in errors unless DUTGND is tied directly to AGND as close as

possible to the ADATE320. For applications that do not distinguish

between DUT ground reference and system analog ground refer-

ence, the DUTGND pin may be connected to the same ground

plane as AGND.

Avoid routing digital lines under the device, because these lines

can couple noise into the device. Generous use of an analog

ground plane under the device shields noise coupling that can

otherwise enter the device. The power supply distribution lines

must provide very wide and low inductance paths to the respective

supply planes. This is especially true for VCC and VEE. Attention

to via inductance is extremely important in these supplies—it can-

not be neglected. Fast switching signals routed in proximity to

the ADATE320 must be adequately shielded, preferably with their

proper ground returns to avoid radiating noise to other parts of the

board. Route such lines as far away as possible from the analog

inputs to the device, such as the AGND, DUTGND, VREF, and

VREFGND reference inputs.

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