ADATE320 datasheet(18/78 Pages) AD

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Data Sheet

ADATE320

SPECIFICATIONS

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Rev. C | 18 of 78

1 PCHx offset is derived from measurements at DAC Code 0xA000 (3.75 V or 50% FS) and DAC Code 0xB333 (4.50 V or 80% FS), with PCLx at DAC Code 0x0000 (−2.5

V). PCLx offset is derived from measurements at DAC Code 0x6000 (1.25 V or −50% FS) and DAC Code 0x4CCC (0.50 V or −80% FS), with PCHx at DAC Code 0xFFFF

(7.5 V).

2 PCHx gain is derived from the measurements at DAC Code 0xA000 (3.75 V or 50% FS) and DAC Code 0xB333 (4.50 V or 80% FS), with PCLx at DAC Code 0x0000

(−2.5 V). PCLx gain is derived from measurements at DAC Code 0x6000 (1.25 V or −50% FS) and DAC Code 0x4CCC (0.50 V or −80% FS), with PCHx at DAC Code

0xFFFF (7.5 V). For example, the ideal gain is ±FS per 2.5 V in all ranges; in Range B, the ideal gain is ±400 µA/V; therefore, 30% error is ±520 µA/V.

PPMU GO/NO-GO COMPARATORS SPECIFICATIONS

Table 8.

Parameter

Min

Typ

Max

Unit

Test Level

Test Conditions/Comments

DC SPECIFICATIONS

Compare Voltage Range

−1.5

+5.0

Input Offset Voltage

−250

+250

Measured at DAC Code 0x4000 (0 V)

Input Offset Voltage TC

±100

μV/°C

Gain

1.0

1.1

V/V

Gain derived from measurements at DAC Code 0x4000 (0.0 V) and

DAC Code 0x8CCC (3.0 V)

Gain TC

±10

ppm/°C

Gain derived from measurements at DAC Code 0x4000 (0.0 V) and

DAC Code 0x8CCC (3.0 V)

Comparator Threshold Resolution

153

µV

Comparator Threshold DNL

±250

µV

After two-point calibration; measured over POHx/POLx range −1.5 V

to +5.0 V; calibration points DAC Code 0x4000 (0.0 V) and DAC Code

0x8CCC (3.0 V)

Comparator Threshold INL

−7

After two-point calibration; measured over POHx/POLx range −1.5 V

to +5.0 V; calibration points DAC Code 0x4000 (0.0 V) and DAC Code

0x8CCC (3.0 V)

DUTGND Voltage Accuracy

−5

±1

Over ±0.1 V range

PPMU EXTERNAL SENSE PINS SPECIFICATIONS

Table 9.

Parameter

Min

Typ

Max

Unit

Test Level

Test Conditions/Comments

DC SPECIFICATIONS

Voltage Range

−1.5

+4.5

PPMU input select, in all states

Leakage

−2

0.0

Tested at −1.5 V and +4.5 V

Maximum Load Capacitance

2000

Capacitive load tolerated at DUTx sense pins

VREF, VREFGND, AND DUTGND REFERENCE INPUT PINS SPECIFICATIONS

Table 10.

Parameter

Min

Typ

Max

Unit

Test Level

Test Conditions/Comments

DC SPECIFICATIONS

VREF Input Voltage Range

2.475

2.500

2.525

Provided externally, VREF = 2.500 V, VREFGND = 0.000 V

VREF Input Bias Current

µA

Tested with 2.500 V applied

DUTGND Input Voltage Range,

Referenced to AGND

−0.1

+0.1

DUTGND Input Bias Current

−10

+10

µA

Tested at −100 mV and +100 mV

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