ADATE320 datasheet(63/78 Pages) AD

No. de pieza	ADATE320

Descripción Electrónicos	1.25 GHz Dual Integrated DCL with PPMU, Level Setting DACs, and On-Chip Calibration Registers

PDF	78 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

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63 / 78 page

Data Sheet

ADATE320

APPLICATIONS INFORMATION

analog.com

Rev. C | 63 of 78

is asserted. After VDD is stable and the RST pin is subsequently

released, a fully clocked reset sequence must follow. This power

supply sequence ensures that analog functions and all level setting

DACs receive the proper configuration information during the digital

partition reset sequence.

The power supplies must be removed in the reverse order.

Note that VREF and the high speed transmission line termination

pins (VTTDx, VTTCx) are all part of the analog partition, but they

are not treated as supplies. VREF can be managed independent

of VCC and VEE, provided its potential never goes outside those of

the VEE and VCC supply buses to prevent ESD protection diodes

from becoming forward biased. The VTTDx and VTTCx pins do not

have this restriction relative to VCC and VEE, but they must never go

outside the absolute maximum ratings as measured with respect to

PGND.

ADATE320 Datasheet(PDF) 63 Page - Analog Devices