MPC8640DEC datasheet(30/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Timing diagrams for FIFO appear in Figure 8 and Figure 9.

Figure 8. FIFO Transmit AC Timing Diagram

FIFO data TXD[7:0], TX_ER, TX_EN setup time to

GTX_CLK

tFITDV

2.0

——ns

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN

hold time

tFITDX

0.5

—

3.0

Table 26. FIFO Mode Receive AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RX_CLK clock period (GMII mode)

tFIR

±100 ppm tolerance on RX_CLK frequency

8.4

8.0

100

RX_CLK clock period (Encoded mode)

tFIR

6.4

8.0

100

RX_CLK duty cycle

tFIRH/tFIR

RX_CLK peak-to-peak jitter

tFIRJ

——

250

Rise time RX_CLK (20%–80%)

tFIRR

—

0.75

Fall time RX_CLK (80%–20%)

tFIRF

—

0.75

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tFIRDV

1.5

——ns

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

tFIRDX

0.5

——ns

Table 25. FIFO Mode Transmit AC Timing Specification (continued)

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

tFIT

tFITH

tFITF

tFITDX

TXD[7:0]

TX_EN

GTX_CLK

TX_ER

tFITDV

tFITR

MPC8640DEC Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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