MPC8640DEC datasheet(69/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

PCI Express

13.3

SerDes Transmitter and Receiver Reference Circuits

Figure 49 shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 49. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express or Serial Rapid IO) in this document based on the application usage:”

•

Section 14, “PCI Express”

•

Section 15, “Serial RapidIO”

Note that external AC Coupling capacitor is required for the above two serial transmission protocols with

the capacitor value defined in specification of each protocol section.

14 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8640.

14.1

DC Requirements for PCI Express SD

n_REF_CLK and

n_REF_CLK

For more information, see Section 13.2, “SerDes Reference Clocks.”

14.2

AC Requirements for PCI Express SerDes Clocks

Table 47 lists AC requirements.

Table 47. SD

n_REF_CLK and SDn_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typical

Max

Units

Notes

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

—

100

—

tREFPJ

Phase jitter. Deviation in edge location with respect to mean

edge location

–50

—

Receiver

Transmitter

SD1_TX

n or

SD2_TX

SD1_TX

n or

SD2_TX

SD1_RX

n or

SD2_RX

SD1_RX

n or

SD2_RX

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