MPC8313ECVRGDDA datasheet(27/100 Pages) FREESCALE

27 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 14 shows the RGMII and RTBI AC timing and multiplexing diagrams.

Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams

Duty cycle for 10BASE-T and 100BASE-TX 3, 5

tRGTH/tRGT

Rise time (20%–80%)

tRGTR

—

0.75

Fall time (20%–80%)

tRGTF

—

0.75

GTX_CLK125 reference clock period

tG12

—8.0

—

GTX_CLK125 reference clock duty cycle

tG125H/tG125

—

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. For example, the subscript of tRGT represents the RTBI (T) receive (RX) clock. Note also that the

notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,

the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is

added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

5. Duty cycle reference is LVDDA/2 or LVDDB/2.

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.

Table 30. RGMII and RTBI AC Timing Specifications (continued)

At recommended operating conditions with LVDDA/LVDDB of 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

GTX_CLK

tRGT

tRGTH

tSKRGT

TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitter)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RXD[8:5][3:0]

RXD[7:4][3:0]

RX_CLK

(At PHY)

tSKRGT

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