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MPC8313ECVRGDDA Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc |
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MPC8313ECVRGDDA Datasheet(HTML) 57 Page - Freescale Semiconductor, Inc |
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57 / 100 page ![]() MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1 Freescale Semiconductor 57 PCI Table 53 shows the PCI AC timing specifications at 33 MHz. Figure 48 provides the AC test load for PCI. Figure 48. PCI AC Test Load Figure 49 shows the PCI input AC timing conditions. Figure 49. PCI Input AC Timing Measurement Conditions Table 53. PCI AC Timing Specifications at 33 MHz Parameter Symbol1 Min Max Unit Notes Clock to output valid tPCKHOV —11 ns 2 Output hold from clock tPCKHOX 2— ns 2 Clock to output high impedance tPCKHOZ —14 ns 2, 3 Input setup to clock tPCIVKH 3.0 — ns 2, 4 Input hold from clock tPCIXKH 0— ns 2, 4 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Output Z0 = 50 Ω NVDD/2 RL = 50 Ω tPCIVKH CLK Input tPCIXKH |
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