TUSB3200 datasheet(42/93 Pages) TI

42 / 93 page

3–2

3.3

Electrical Characteristics Over Recommended Operating Conditions (unless

otherwise noted)

PARAMETER

TEST

CONDITIONS

MIN

TYP

MAX

UNITS

3.3-V TTL/LVCMOS (MCLKO, MCLKO2, PLLO,

PUR, RSTO)

DVDD–

0.5

VOH

High-level output

voltage

5-V compatible TTL/LVCMOS (CSCLK, CSYNC,

CDATO, CDATI, CRESET, CSCHNE, P1, P3)

IOH = –4 mA

DVDD–

0.5

3.3-V – 5-V CMOS level shifting (PWMO)

DVDD–

0.5

3.3-V TTL/LVCMOS (MCLKO, MCLKO2, PLLO,

PUR, RSTO)

0.5

VOL

Low-level output voltage

5-V compatible TTL/LVCMOS (CSCLK, CSYNC,

CDATO, CDATI, CRESET, CSCHNE, P1, P3)

IOL = 4 mA

0.5

3.3-V – 5-V TTL level shifting, open drain (SCL,

SDA)

0.5

3.3-V – 5-V CMOS level shifting (PWMO)

0.5

3.3-V TTL/LVCMOS (MCLKO, MCLKO2, PLLO,

PUR, RSTO)

±20

IOZ

High-impedance output

current

5-V compatible TTL/LVCMOS (CSCLK, CSYNC,

CDATO, CDATI, CRESET, CSCHNE, P1, P3)

±20

µA

3.3-V – 5-V TTL level shifting, open drain (SCL,

SDA)

±20

3.3-V TTL/LVCMOS (EXTEN, MRESET, TEST)

–20

IIL

Low-level input current

5-V compatible TTL/LVCMOS (CSCLK, CSYNC,

CDATO, CDATI, CRESET, CSCHNE, P1, P3,

PLLOEN, XINT)

VI = VIL

–20

µA

5-V – 3.3-V TTL level shifting (MCLKI, MCLKI2,

SDA)

–20

3.3-V TTL/LVCMOS (EXTEN, MRESET, TEST)

IIH

High-level input current

5-V compatible TTL/LVCMOS (CSCLK, CSYNC,

CDATO, CDATI, CRESET, CSCHNE, P1, P3,

PLLOEN, XINT)

VI = VIH

µA

5-V–3.3-V TTL level shifting (MCLKI, MCLKI2,

SDA)

Digital supply voltage , DVDD

IDD

Input supply current

Secondary digital supply voltage, DVDDS

Analog supply voltage, AVDD

TUSB3200 Datasheet(PDF) 42 Page - Texas Instruments

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