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TUSB3200 Datasheet(PDF) 88 Page - Texas Instruments |
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TUSB3200 Datasheet(HTML) 88 Page - Texas Instruments |
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88 / 93 page  A–40 A.5.7 Miscellaneous Registers This section describes the memory-mapped registers used for the control and operation of miscellaneous functions in the TUSB3200 device. The registers include the USB out endpoint interrupt register, the USB in endpoint interrupt register, the interrupt vector register, the global control register, and the memory configuration register. A.5.7.1 USB Out Endpoint Interrupt Register (OEPINT – Address FFB4h) The USB out endpoint interrupt register contains the interrupt pending status bits for the USB out endpoints. These bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for diagnostic purposes only. Bit 7 6 5 4 3 2 1 0 Mnemonic OEPI7 OEPI6 OEPI5 OEPI4 OEPI3 OEPI2 OEPI1 OEPI0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 OEPI(7:0) Out endpoint interrupt The out endpoint interrupt status bit for a particular USB out endpoint is set to a 1 by the UBM when a successful completion of a transaction occurs to that out endpoint. When a bit is set, an interrupt to the MCU will be generated and the corresponding interrupt vector will result. The status bit will be cleared when the MCU writes to the interrupt vector register. These bits do not apply to isochronous out endpoints. A.5.7.2 USB In Endpoint Interrupt Register (IEPINT – Address FFB3h) The USB in endpoint interrupt register contains the interrupt pending status bits for the USB in endpoints. These bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for diagnostic purposes only. Bit 7 6 5 4 3 2 1 0 Mnemonic IEPI7 IEPI6 IEPI5 IEPI4 IEPI3 IEPI2 IEPI1 IEPI0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 IEPI(7:0) In endpoint interrupt The in endpoint interrupt status bit for a particular USB in endpoint is set to a 1 by the UBM when a successful completion of a transaction occurs to that in endpoint. When a bit is set, an interrupt to the MCU will be generated and the corresponding interrupt vector will result. The status bit will be cleared when the MCU writes to the interrupt vector register. These bits do not apply to isochronous in endpoints. |
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