ATmega16HVB datasheet(84/273 Pages) ATMEL

84 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

Signal description (internal signals):

count

Increment or decrement TCNTn by 1.

clk

Timer/Counter clock, referred to as clk

Tn in the following.

top

Signalize that TCNTn has reached maximum value.

The counter is incremented at each timer clock (clk

Tn) until it passes its TOP value and then

restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0 bits

located in the Timer/Counter Control Register (TCCRnA). For more details about counting

sequences, see ”Timer/Counter Timing Diagrams” on page 89. clk

Tn can be generated from an

external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock

source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be

accessed by the CPU, regardless of whether clk

Tn is present or not. A CPU write overrides (has

priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOVn) is

set when the counter reaches the maximum value and it can be used for generating a CPU

interrupt.

17.5

Modes of Operation

The mode of operation is defined by the Timer/Counter Width (TCWn), Input Capture Enable

(ICENn) and the Waveform Generation Mode (WGMn0)bits in ”TCCRnA – Timer/Counter n

Control Register A” on page 94. Table 17-2 on page 84 shows the different Modes of Operation.

17.5.1

Normal 8-bit Mode

In the normal mode, the counter (TCNTnL) is incrementing until it overruns when it passes its

maximum 8-bit value (MAX = 0xFF) and then restarts from the bottom (0x00), see Table 17-2 on

page 84 for bit settings. The Overflow Flag (TOVn) will be set in the same timer clock cycle as

the TCNTnL becomes zero. The TOVn Flag in this case behaves like a ninth bit, except that it is

only set, not cleared. However, combined with the timer overflow interrupt that automatically

clears the TOVn Flag, the timer resolution can be increased by software. There are no special

cases to consider in the Normal 8-bit mode, a new counter value can be written anytime. The

Output Compare Unit can be used to generate interrupts at some given time.

17.5.2

Clear Timer on Compare Match (CTC) 8-bit Mode

In Clear Timer on Compare or CTC mode, the OCRnA Register is used to manipulate the coun-

ter resolution, see Table 17-2 on page 84 for bit settings. In CTC mode the counter is cleared to

Table 17-2.

Modes of Operation

Mode

ICENn

TCWn

WGMn0

Timer/Counter Mode

of Operation

TOP

Update of

OCRx at

TOV Flag

Set on

Normal 8-bit Mode

0xFF

Immediate

MAX (0xFF)

8-bit CTC

OCRnA

Immediate

MAX (0xFF)

16-bit Mode

0xFFFF

Immediate

MAX (0xFFFF)

16-bit CTC

OCRnB,

OCRnA

Immediate

MAX (0xFFFF)

8-bit Input Capture

mode

0xFF

–

MAX (0xFF)

16-bit Input Capture

mode

0xFFFF

–

MAX (0xFFFF)

ATmega16HVB Datasheet(PDF) 84 Page - ATMEL Corporation

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