ATmega16HVB datasheet(25/273 Pages) ATMEL

25 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

System Clock and Clock Options

9.1

Clock Systems and their Distribution

Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in ”Power Manage-

ment and Sleep Modes” on page 35. The clock systems are detailed below.

Figure 9-1.

Clock Distribution

9.1.1

CPU Clock – clk

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

9.1.2

I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules. The I/O clock is also used by the Exter-

nal Interrupt module, but note that some external interrupts are detected by asynchronous logic,

allowing such interrupts to be detected even if the I/O clock is halted.

9.1.3

Flash Clock – clk

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

Ultra Low Power

RC Oscillator

Watchdog Timer

Battery Protection

Reset Logic

CPU

CORE

RAM

FLASH and

EEPROM

Voltage

ADC

Other I/O

Modules

Coulomb Counter

ADC

AVR

Clock Control

Fast RC

Oscillator

clk

CPU

clk

FLASH

clk

VADC

clk

I/O

1/4

System Clock

Prescaler

VADC

Prescaler

Oscillator Sampling

Interface

Slow RC

Oscillator

clk

CCADC

TWI Disconnect

delay

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