Rev 1.00

March 22, 2010

13

HT45B0K

SPI to USB Bridge

1: Error has occurred during endpoint 0 FIFO is accessed.

The ERR bit is used to indicate that there are some errors occurred during

endpoint 0 FIFO is accessed. This bit is set by SIE and should be cleared by

firmware.

Bit 0

ASET: Device Address update control

0: device address is updated immediately when the AWR register is written.

1: device address is updated after the device IN token data has been read

(SETUP stage finished).

The ASET bit is used to configure the SIE to automatically update the device

address with the value stored in the AWR register. When this bit is set to 1

by firmware, the SIE will update the device address with the value stored

in the AWR register after the USB host has successfully read the data from

the device by IN token. Otherwise, when this bit is cleared to 0, the SIE will

update the device address immediately after an address is written to the AWR

register.

MISC Register

The MISC register contains the commands to control the desired endpoint FIFO action along with

the status to show the condition of the desired endpoint FIFO. The MISC register will be cleared by

a USB reset signal.

MISC Register

Bit

7

6

5

4

3

2

1

0

Name

LEN0

READY

SETCMD

――

CLEAR

TX

REQUEST

R/W

R/W

R

R/W

――

R/W

R/W

R/W

POR

0

x

1

――

00

0

“x” means unknown.

Bit 7

LEN0: zero-length packet indication flag for Endpoint 0

0: no operation.

1: a zero-length packet is sent from the USB host.

If this bit is set to 1, it indicates that a 0-sized packet is sent from a USB host. This bit

should be cleared by the application program or by the next valid SETUP token.

Bit 6

READY: Endpoint FIFO Ready indication flag

0: the desired endpoint FIFO is not ready.

1: the desired endpoint FIFO is ready.

This bit is used to indicate whether the desired endpoint FIFO is ready to operate or not.

Bit 5

SETCMD: SETUP command indication flag

0: the data in the endpoint 0 FIFO is not SETUP token.

1: the data in the endpoint 0 FIFO is SETUP token.

This bit is used to indicate whether the data in the Endpoint 0 FIFO is SETUP token or

not. It is set by hardware and cleared by firmware.

Bit 4~3

Unimplemented, read as “0”.

Bit 2

CLEAR: clear requested FIFO

0: no operation.

1: clear the requested endpoint FIFO.

This bit is used by MCU to clear the requested FIFO, even if the FIFO is not ready. If

user wants to clear the current requested Endpoint FIFO, the CLEAR bit should be set to

1 to generate a positive pulse with 2μs pulse width and then clear this bit to zero.

Bit 1

TX: Direction of data transfer between the MCU and the endpoint FIFO