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MC68HC705MC4MP Datasheet(PDF) 40 Page - Freescale Semiconductor, Inc |
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MC68HC705MC4MP Datasheet(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 180 page ![]() Interrupts MC68HC705MC4 — Rev. 2.0 Interrupts Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is completed. When the current instruction is completed, the processor checks all pending hardware interrupts. If interrupts are not masked (I-bit in the condition code register is clear), and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed, the CPU puts the register contents on the stack, sets the I-bit in the CCR, and fetches the address of the corresponding interrupt service routine from the vector table at locations $0FF0 through $0FFF. If more than one interrupt is pending when the interrupt vector is fetched, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the CPU state to be recovered from the stack and normal processing to resume at the next Table 4-1. Vector Addresses for Interrupts and Reset Register Flag Name Interrupts CPU Interrupt Vector Address N/A N/A Reset RESET $0FFE–$0FFF N/A N/A Software SWI $0FFC–$0FFD ISCR REQ External Interrupt IRQ $0FFA–$0FFB TSR ICF2 Timer Input Capture 2 TIMER $0FF8–$0FF9 TSR ICF1 Timer Input Capture 1 TIMER $0FF6–$0FF7 TSR OCF Timer Output Compare* TIMER $0FF4–$0FF5 TSR TOF Timer Overflow* TIMER $0FF4–$0FF5 SCSR Various SCI SCI $0FF2–$0FF3 CTCSR CTOF Core Timer Overflow* CTIMER $0FF0–$0FF1 CTCSR RTIF Core Timer Real Time* CTIMER $0FF0–$0FF1 * Vector is shared Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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