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ICS9148-36 Datasheet(PDF) 5 Page - Integrated Device Technology |
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ICS9148-36 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 16 page ![]() 5 ICS9148-36 Byte0: Functionality and Frequency Select Register (default = 0) Serial Configuration Command Bitmap I2C is a trademark of Philips Corporation Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle. Note: PWD = Power-Up Default t i Bn o i t p i r c s e DD W P 7 t i B n o i t a r e p o l a m r o n r o f 0 e b t s u M 0 n o i t a l u d o M m u r t c e p S d a e r p S % 5 2 . 0 ± - 0 n o i t a l u d o M m u r t c e p S d a e r p S % 6 . 0 ± - 1 t i B 4 : 6 4 t i B 5 t i B 6 t i B 1 1 1 0 1 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 k c o l C U P C 0 0 1 5 2 . 5 9 3 . 3 8 5 7 5 7 5 . 8 6 8 . 6 6 0 6 I C P 3 . 3 3 5 7 . 1 3 3 . 3 3 0 3 5 . 7 3 5 2 . 4 3 4 . 3 3 0 3 P G A 6 . 6 6 5 . 3 6 6 . 6 6 0 6 5 7 5 . 8 6 8 . 6 6 0 6 1 e t o N 3 t i B , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r F - 0 s t u p n I d e h c t a L ) e v o b a ( 4 : 6 t i B y b d e t c e l e s s i y c n e u q e r F - 1 0 2 t i B n o i t a r e p o l a m r o n r o f 0 e b t s u M 0 . e p y t d a e r p s r e t n e c m u r t c e p S d a e r p S - 0 . e p y t d a e r p s n w o d m u r t c e p S d a e r p S - 1 1 t i B l a m r o N - 0 d e l b a n E m u r t c e p S d a e r p S - 1 0 0 t i B g n i n n u R - 0 s t u p t u o l l a e t a t s i r T - 1 0 Byte 1: CPU,Active/Inactive Register (1 = enable, 0 = disable) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Notes: 1. Inactive means outputs are held LOW and are disabled from switching. t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 1 ) d e v r e s e R ( 6 t i B- X # 2 S F 5 t i B- X # 1 S F 4 t i B0 41 ) t c a n I / t c A ( 2 1 M A R D S 3 t i B- 1 ) d e v r e s e R ( 2 t i B1 41 ) t c a n I / t c A ( 2 K L C U P C 1 t i B3 41 ) t c a n I / t c A ( 1 K L C U P C 0 t i B4 41 ) t c a n I / t c A ( 0 K L C U P C t i B# n i PD W Pn o i t p i r c s e D 7 t i B- X 5 . 2 _ # 3 . 3 U P C 6 t i B7 1 ) t c a n I / t c A ( F _ K L C I C P 5 t i B- X # 0 S F 4 t i B3 11 ) t c a n I / t c A ( 4 K L C I C P 3 t i B2 11 ) t c a n I / t c A ( 3 K L C I C P 2 t i B1 11 ) t c a n I / t c A ( 2 K L C I C P 1 t i B0 11 ) t c a n I / t c A ( 1 K L C I C P 0 t i B8 1 ) t c a n I / t c A ( 0 K L C I C P Byte 2: PCIActive/Inactive Register (1 = enable, 0 = disable) |
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