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MPC5125YVN400 Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc |
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MPC5125YVN400 Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc |
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77 / 94 page ![]() Electrical and Thermal Characteristics MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 77 Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 43. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) 1 NOTES: 1 Output timing is specified at a nominal 50 pF load. Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.37 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.38 3 Slave select clock delay 1.0 — ns A20.39 4 Input data setup time 1.0 — ns A20.40 5 Input data hold time 1.0 — ns A20.41 6 Output data valid after SS —14.0 ns A20.42 7 Output data valid after SCK — 14.0 ns A20.43 8 Slave disable lag time 0.0 — ns A20.44 9 Minimum sequential transfer delay = 2 IP bus clock cycle time 30.0 — — A20.45 SCK (CLKPOL=0) SCK (CLKPOL=1) MOSI Output Output Output SS Output MISO Input 1 22 8 9 3 4 5 6 6 7 7 11 10 10 11 |
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