REV. A

AD7013

–11–

RECEIVE SECTION

The receive section consists of I and Q receive channels, each

comprising of a simple switched-capacitor filter followed by a 15-bit

sigma-delta ADC. The data is available on a 16-bit serial interface,

interfacing easily to most DSPs. On-board digital filters, which

form part of the sigma-delta ADCs, also perform system level

filtering. A choice of two digital filter responses are available,

optimized for either

π/4 DQPSK digital mode or the existing analog

cellular system. For digital mode, Root-Raised Cosine digital filters

can be selected; whereas for analog mode, digital filters with a

–3 dB point of 11.4 kHz can be selected. Their amplitude and

phase response characteristics provide excellent adjacent channel

rejection. A means is also provided to calibrate either on-chip or

receive path offsets in both the I and Q channels. The receive

section is also provided with a low power sleep mode, drawing only

minimal current between receive bursts.

Switched Capacitor Input

The receive section analog front-end is sampled at MCLK/4 by a

switched-capacitor filter. The filter has a zero at MCLK/8 as

shown in Figure 8a. The receive channel also contains a digital

low-pass filter (further details are contained in the following

section) which operates at a clock frequency of MCLK/8. Due to

the sampling nature of the digital filter, the pass band is repeated

about the operating clock frequency (MCLK/8) and at multiples of

the clock frequency (Figure 8b). Because the first null of the

switched-capacitor filter coincides with the first image of the digital

filter, this image is attenuated by an additional 30 dBs (Figure 8c)

further simplifying the external antialiasing requirements. A simple

R-C Network can be used to attenuate the digital filter image at

MCLK/8 as shown in Figure 9.

MCLK/8

MCLK/4

MCLK/2

MHz

MHz

MHz

0dBs

0dBs

0dBs

–30

dBs

MAX

FRONT-END

ANALOG

FILTER

TRANSFER

DIGITAL

FILTER

TRANSFER

FUNCTION

SYSTEM

FILTER

TRANSFER

FUNCTION

MCLK/8

MCLK/4

MCLK/2

MCLK/8

MCLK/4

MCLK/2

Figure 8. Switched Capacitor and Digital Filter Transfer

Functions

a.

b.

c.

Receive Channel Differential Inputs

The receive channel uses differential inputs to interface more easily

to IQ demodulators and also to provide common-mode noise

rejection. However, if required the receive channel inputs can also

be configured for single ended operation. The primary and

auxiliary channels have similar performance and either can be used

for differential operation or single-ended operation. The CR12

control bit determines whether the primary or auxiliary inputs are

connected to the differential inputs of the sigma-delta modulator.

Figure 9 illustrates an antialiasing filter comprised of a single pole

RC network with a –3 dB frequency of 159 kHz. The low-pass

filter provides sufficient rejection at images of the FIR digital filter

illustrated in Figure 10c.

For single ended operation, the inverting input should be con-

nected to a bias voltage and the noninverting input should swing

±1.3 V around this bias voltage in order to exercise the entire ADC

range. In applications where the full

±1.3 V range is not required,

the on-chip 1.23 V reference can be used to provide the bias

voltage. For instance as in Figure 10, an OP295 rail-to-rail low

power op amp is used to buffer the BYPASS pin in order to

generate a 1.23 V

The V

thereby setting the single-ended input range equal to 0 V to 2.46 V.

Also with the addition of an attenuator circuit the input range can

be expanded to 0 V to 4.92 V as shown on the second ADC

channel. If the inverting input is tied to AGND, then only half the

ADC range is available.

AD7013

0.01nF

QRx

IRx

10nF

BYPASS

I

T

Q

Q

IQ

DEMODULATOR

0.01nF

Figure 9. External RC Network for Differential Signals

AD7013

0.1nF

AUX IRx

AUX QRx

AUX QRx

AUX IRx

0.1nF

10nF

BYPASS

0 TO 4.92 VOLTS

5V

1.23 VOLTS

295

0 TO 2.46 VOLTS

Figure 10. External RC Network for Single-Ended Signals