–16–

REV. A

AD7013

PCB Layout Considerations

The use of an analog ground plane is recommended, where the

ground plane extends around the analog circuitry. Both AGND and

DGND should be externally tied together and connected to the

analog ground plane.

Good power supply decoupling is very important for best ADC

performance. A 0.1

µF ceramic decoupling capacitor should be

connected between V

ment of the capacitor (surface mount if possible) is important and

should be placed as close to the pin of the device as is physically

possible. This is also applied to the V

decoupling can lead to a degradation in ADC offsets and SNR.

The Bypass pin should be decoupled to the ground plane using a

10 nF capacitor. Large capacitor values are not recommended as

this can cause the reference not to reach its final value, on power

up, before ADC autocalibration has commenced.

Capacitive loading of digital outputs should be minimized as much

as possible if power dissipation is a critical factor. The charging

and discharging of external load capacitances can be a significant

contribution to power dissipation, especially when the AD7013 is in

a low power sleep mode as the DxCLK remains active.

10-BIT

AUX DAC1

AGND

AGND

AGND

AGND

8-BIT

AUX DAC2

8-BIT

AUX DAC3

FULL–SCALE

ADJUST

CONTROL

(1.23V)

AD7013

Figure 22. AUX DACs

AD7013

AUX DAC1,

AUX DAC2

OR AUX DAC3

FS ADJUST

10nF

BYPASS

+5V

OP-295

18k

Ω

AUX DAC

10-BIT

8-BIT

Figure 23. External Op Amp Circuitry to Extend Output

Voltage Range

Low Sampling Rate (CR10 = 0)

The timing diagram for the receive interface is shown in Figure 4.

The output word rate per channel is equal to 48.6 kHz (MCLK/

128) which corresponds to two times the symbol rate. The low

sampling rate operates in a similar manner to that described for the

high sampling rate.

AUXILIARY DACs

One 10-bit auxiliary DAC and two 8-bit auxiliary DACs are

provided for extra control functions such as automatic gain control,

automatic frequency control and power control. Figure 22

illustrates a simplified block diagram of the auxiliary DACs. The

AUX DACs consist of high impedance current sources, designed to

operate at very low currents while maintaining their DC accuracy.

The DACs are designed using a current segmented architecture.

The bit currents corresponding to each digital input are either

routed to the analog output (bit = 1) or to AGND (bit = 0).

Each of the auxiliary DACs has independent low power sleep

modes. The command register has three control bits CR17, CR16

and CR15 which control AUX DAC1, AUX DAC2 and AUX

DAC3 respectively. A logic 0 represents low power sleep mode and

a logic 1 represents normal operation.

The full-scale currents of the auxiliary DACs are controlled by a

single external resistor, R

pin and AGND. The relationship between full-scale current and

R

10-Bit AUX DAC

AUX DAC

8-Bit AUX DACs

AUX DAC

By using smaller values of R

scale current, improved INL and DNL performance is possible as

shown in Table V.

Digital Interface

Communication with the Command register, auxiliary DACs, ADC

offset registers and ADC vernier is accomplished via the 3-pin serial

interface. Either one of two loading formats may be used to write

to any of the AD7013’s internal registers. The first format consists

of a single 16-bit serial word to write to any internal register (Table

III). The second format consists of five 16-bit serial words, where

only the last 6 bits in each 16-bit word are used to load five 2-bit

data nibbles. The load sequence for this format is given is Table IV.

The second format is only enable when the Register Address 3 is

used as the destination register as shown in Table I.

18 k

Ω

–1.45

+1.83

9 k

Ω

+1.22

+1.59

4.5 k

Ω

+1.18

+1.38

Worst Case

Worst Case

R

SET

INL (LSBs)

DNL (LSBs)