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INTEDG Datasheet(PDF) 173 Page - Microchip Technology |
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INTEDG Datasheet(HTML) 173 Page - Microchip Technology |
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173 / 478 page ![]() 2010-2012 Microchip Technology Inc. DS41414D-page 173 PIC16(L)F1946/47 FIGURE 16-4: ANALOG INPUT MODEL FIGURE 16-5: ADC TRANSFER FUNCTION Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k . This is required to meet the pin leakage specification. CPIN VA Rs Analog 5 pF VDD VT 0.6V VT 0.6V I LEAKAGE(1) RIC 1k Sampling Switch SS Rss CHOLD = 10 pF VSS/VREF- 6V Sampling Switch 5V 4V 3V 2V 567 8 9 10 11 (k ) VDD Legend: CPIN VT I LEAKAGE RIC SS CHOLD = Input Capacitance = Threshold Voltage = Leakage current at the pin due to = Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance various junctions RSS Note 1: Refer to Section 30.0 “Electrical Specifications” . RSS = Resistance of Sampling Switch Input pin 3FFh 3FEh 3FDh 3FCh 03h 02h 01h 00h Full-Scale 3FBh 0.5 LSB VREF- Zero-Scale Transition VREF+ Transition 1.5 LSB Full-Scale Range Analog Input Voltage |
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