INTEDG datasheet(201/478 Pages) MICROCHIP

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DS41414D-page 201

PIC16(L)F1946/47

21.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

21.4

Timer1 Oscillator

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins T1OSI (input) and T1OSO

(amplifier output). This internal circuit is to be used in

conjunction with an external 32.768 kHz crystal.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator will

continue to run during Sleep.

21.5

Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If the external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 21.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

21.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

21.6

Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 Gate Enable.

Timer1 gate can also be driven by multiple selectable

sources.

21.6.1

TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 21-3 for timing details.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to using Timer1. A

suitable delay, similar to the OST delay

can be implemented in software by

clearing the TMR1IF bit, then presetting

the TMR1H:TMR1L register pair to

FC00h. The TMR1IF flag will be set when

1024 clock cycles have elapsed, thereby

indicating that the oscillator is running and

is reasonably stable.

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

TABLE 21-3:

TIMER1 GATE ENABLE

SELECTIONS

T1CLK

T1GPOL

T1G

Timer1 Operation



Counts



Holds Count



Holds Count



Counts

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