AM79C960KCW datasheet(52/127 Pages) AMD

52 / 127 page

P R E L I M I N A R Y

AMD

1-394

Am79C960

Shared Memory Mode

Address PROM Cycles

The Address PROM is a small (16 bytes) 8-bit PROM

connected to the PCnet-ISA controller Private Data Bus

(PRDB). The PCnet-ISA controller will support only 8-bit

ISA I/O bus cycles for the address PROM; this limitation

is transparent to software and does not preclude 16-bit

software I/O accesses. An access cycle begins with the

Permanent Master driving AEN LOW, driving the ad-

dresses valid, and driving

IOR active. The PCnet-ISA

controller detects this combination of signals and arbi-

trates for the Private Data Bus if necessary. IOCHRDY

is always driven LOW during address PROM accesses.

When the Private Data Bus becomes available, the

PCnet-ISA controller drives

APCS active, releases

IOCHRDY, turns on the data path from PRD0-7, and en-

ables the SD0-7 drivers (but not SD8-15). During this

bus cycle,

IOCS16 is not driven active. This condition is

maintained until

IOR goes inactive, at which time the ac-

cess cycle ends. Data is removed from SD0-7 within

30 ns.

The PCnet-ISA controller will perform 8-bit ISA bus cy-

cle operation for all resources (registers, PROMs,

SRAM) if

SBHE has been left unconnected, such as in

the case of an 8-bit system like the PC/XT.

Ethernet Controller Register Cycles

Ethernet controller registers (RAP, RDP, ISACSR) are

naturally 16-bit resources but can be configured to oper-

ate with 8-bit bus cycles provided the proper protocol is

followed. If

IOCS16 has never gone HIGH since RE-

SET, then all controller register bus cycles will be 8-bit

only. This situation would occur if the

IOCS16 pin is dis-

connected from the ISA bus and tied to ground. This

means on a read, the PCnet-ISA controller will only drive

the low byte of the system data bus; if an odd byte is ac-

cessed, it will be swapped down. The high byte of the

system data bus is never driven by the PCnet-ISA con-

troller under these conditions. On a write, the even byte

is placed in a holding register. An odd-byte write is inter-

nally swapped up and augmented with the even byte in

the holding register to provide an internal 16-bit write.

This allows the use of 8-bit I/O bus cycles which are

more likely to be compatible with all clones, but requires

that both bytes be written in immediate succession. This

is accomplished simply by treating the PCnet-ISA con-

troller controller registers as 16-bit software resources.

The motherboard will convert the 16-bit accesses done

by software into two sequential 8-bit accesses, an even-

byte access followed immediately by an odd-byte

access.

An access cycle begins with the Permanent Master driv-

ing AEN LOW, driving the address valid, and driving

IOR

IOW active. The PCnet-ISA controller detects this

combination of signals and drives IOCHRDY LOW.

IOCS16 will also be driven LOW if 16-bit I/O bus cycles

are enabled. When the register data is ready, IOCHRDY

will be released HIGH. This condition is maintained until

IOR or IOW goes inactive, at which time the bus cycle

ends.

The PCnet-ISA controller will perform 8-bit ISA bus cy-

cle operation for all resources (registers, PROMs,

SRAM) if

SBHE has been left unconnected, such as in

the case of an 8-bit system like the PC/XT.

RESET Cycles

A read to the reset address causes an PCnet-ISA con-

troller reset. This has the same effect as asserting the

RESET pin on the PCnet-ISA controller, such as hap-

pens during a system power-up or hard boot. The

subsequent write cycle needed in the NE2100 LANCE-

based family of Ethernet cards is not required but does

not have any harmful effects.

IOCS16 is not asserted in

this cycle.

ISA Configuration Register Cycles

The ISA configuration register is accessed by placing

the address of the desired register into the RAP and

reading the IDP. The ISACSR bus cycles are identical

to all other PCnet-ISA controller register bus cycles.

Boot PROM Cycles

The Boot PROM is an 8-bit PROM connected to the

PCnet-ISA controller Private Data Bus (PRDB), and can

occupy up to 64 Kbytes of address space. In Shared

Memory Mode, an external address comparator is re-

sponsible for asserting

BPAM to the PCnet-ISA

controller.

BPAM is intended to be a perfect decode of

the boot PROM address space, i.e.

REF, LA17-23,

SA14-16 for a 16 Kbyte PROM. The LA bus must be

latched with BALE in order to provide stable signal for

BPAM. REF inactive must be used by the external logic

to gate boot PROM address decoding. This same logic

must assert

MEMCS16 to the ISA bus if 16-bit Boot

PROM bus cycles are desired.

The PCnet-ISA controller assumes 16-bit ISA memory

bus cycles for the boot PROM. A 16-bit boot PROM bus

cycle begins with the Permanent Master driving the ad-

dresses valid,

REF inactive, and SMEMR active. (AEN

is not involved in memory cycles). External hardware

would assert

BPAM and MEMCS16. The PCnet-ISA

controller detects this combination of signals, drives

IOCHRDY LOW, and reads two bytes out of the boot

PROM. The data bytes read from the PROM are driven

by the PCnet-ISA controller onto SD0-15 and IOCHRDY

is released. This condition is maintained until

MEMR

goes inactive, at which time the access cycle ends.

The PCnet-ISA controller can be made to support only

8-bit ISA memory bus cycles for the boot PROM. This

can be accomplished by asserting

BPAM and SMAM si-

multaneously; the PCnet-ISA controller would respond

using 8-bit ISA memory bus cycles only. Since this is an

illegal situation for simple address decoders, the exter-

nal address decoder must artificially drive

SMAM LOW

when the (8-bit) boot PROM address space is being ac-

cessed. In this case,

MEMCS16 must not be asserted.

AM79C960KCW Datasheet(PDF) 52 Page - Advanced Micro Devices

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