AM79C960KCW datasheet(65/127 Pages) AMD

65 / 127 page

P R E L I M I N A R Y

AMD

1-407

Am79C960

Transmit

Mode

Select

(AUI

Mode only)

LRT

Low Receive Threshold. When

LRT = “1”, the internal twisted

pair receive thresholds are re-

duced by 4.5 dB below the

standard 10BASE-T value (ap-

proximately

3/5)

and

the

unsquelch threshold for the RXD

circuit will be 180–312 mV peak.

When LRT = “0”, the unsquelch

threshold for the RXD circuit will

the

standard

10BASE-T

value, 300–520 mV peak.

In either case, the RXD circuit

post squelch threshold will be

one

half

the

unsquelch

threshold.

This bit only has meaning when

the 10BASE-T network interface

is selected.

Read/write accessible only when

STOP bit is set. Cleared by

RESET.

TSEL

Transmit Mode Select. TSEL

controls the levels at which the

AUI drivers rest when the AUI

transmit port is idle. When TSEL

= 0, DO+ and DO- yield “zero” dif-

ferential to operate transformer

coupled loads (Ethernet 2 and

802.3). When TSEL = 1, the DO+

idles at a higher value with re-

spect to DO- , yielding a logical

HIGH state (Ethernet 1).

This bit only has meaning when

the AUI network interface is

selected.

Read/write accessible only when

STOP bit is set. Cleared by

RESET.

8-7

PORTSEL

Port Select bits allow for software

[1:0]

controlled selection of the net-

work medium. Medium selection

can be over ridden by

the

MAUSEL pin if the XMAUSEL bit

in the ISA Configuration Register

is set.

Read/write accessible only when

STOP bit is set. Cleared by

RESET.

The network port configuration

are as follows:

PORTSEL[1:0]

Network Port

0 0

AUI

0 1

10BASE-T

1 0

GPSI*

1 1

Reserved

*Refer to the section on General Purpose Serial Interface for

detailed information on accessing GPSI.

INTL

Internal Loopback. See the de-

scription of LOOP, CSR15.2.

Read/write accessible only when

STOP bit is set.

DRTY

Disable Retry. When DRTY = “1”,

PCnet-ISA controller will attempt

only one transmission. If DRTY =

“0”, PCnet-ISA controller will

attempt 16 retry attempts before

signaling a retry error.

Read/write accessible only when

STOP bit is set.

FCOLL

Force Collision. This bit allows

the collision logic to be tested.

PCnet-ISA controller must be in

internal loopback for FCOLL to

be valid. If FCOLL = “1”, a colli-

sion

will

forced

during

loopback transmission attempts;

a Retry Error will ultimately re-

sult. If FCOLL = “0”, the Force

Collision logic will be disabled.

Read/write accessible only when

STOP bit is set.

DXMTFCS

Disable Transmit CRC (FCS).

When DXMTFCS = 0, the trans-

mitter will generate and append a

FCS to the transmitted frame.

When DXMTFCS = 1, the FCS

logic is allocated to the receiver

and no FCS is generated or sent

with the transmitted frame.

AM79C960KCW Datasheet(PDF) 65 Page - Advanced Micro Devices

AM79C960KCW Datasheet(HTML) 65 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL