AS3607 datasheet(57/71 Pages) AMSCO

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AS3606 AS3607 2v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 48. First Interrupt Register

Name

Base

Default

IRQENRD_0

2-wire serial

00h

Offset: 23h

First Interrupt Register

Please be aware that writing to this register will enable/disable the corresponding

interrupts, while reading gets the actual interrupt status and will clear the register at the

same time. It is not possible to read back the interrupt enable/disable settings. This register is

reset at a VDD27-POR or XRES input.

Bit

Bit Name

Default

Access

Bit Description

CVDD1_SD

Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD1

occurs

0: disable

1: enable

CVDD1_under

This bit is set when a –5% under-voltage at CVDD1 occurs

CVDD1_IRQ

Enables interrupt for over-voltage/under-voltage supervision of CVDD1

0: disable

1: enable

CVDD1_over

This bit is set when a +8% over-voltage at CVDD1 occurs

CVDD2_SD

Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD2

occurs

0: disable

1: enable

CVDD2_under

This bit is set when a –5% under-voltage at CVDD2 occurs

CVDD2_IRQ

Enables interrupt for over-voltage/under-voltage supervision of CVDD2

0: disable

1: enable

CVDD2_over

This bit is set when a +8% over-voltage at CVDD2 occurs

CVDD3_SD

Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD3

occurs

0: disable

1: enable

CVDD3_under

This bit is set when a –5% under-voltage at CVDD3 occurs

CVDD3_IRQ

Enables interrupt for over-voltage/under-voltage supervision of CVDD3

0: disable

1: enable

CVDD3_over

This bit is set when a +8% over-voltage at CVDD3 occurs

1:0

n/a

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