ZIOL2201 datasheet(29/91 Pages) ETC2

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ZIOL2xxx – IC Family

IO-Link compliant HV Line Driver IC Family

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

29 of 90

Depending on the IC configuration the any exception or stored exception can cause the INT_L pin to logic low. As

shown in Figure 3.8 INT_L can follow the state signals (internal exceptions) or the stored exception which is also

depending on the IC configuration.

3.3.6.

Channel Locking in Master/Device Mode

There are three independent lock mechanisms implemented. For each channel (COM and AUX) a separate lock

can be generated if an over-current at the high side or low side switch has occurred. Therefore it is implied that for

the considered switch a current limit had been configured. The third lock mechanism which is affecting both

channels is related to over-temperature situations.

As regards the IC operation as IO-Link master or device PHY (master/device mode, refer to chapter 3.3.2) the

lock mechanisms of both channels are really separated or coordinated as following described:

Master

12 mode (COM and AUX driver work in parallel – Tandem Mode):

 Assumed that both channels (COM and AUX) are enabled and the configuration flag

BOTH_CHANNEL_LOCK (register[14]) is set (=1), both HS or both LS driver of both channels need to be

overloaded simultaneously for longer as a configured time in order to generate an IC-internal overload

exception which is indicated at the INT_L pin (logic low).

 In the case the IC works in tandem mode and the configuration flag BOTH_CHANNEL_LOCK (register 14)

is set (=1), but only one of the channels (COM or AUX) is enabled, the protection of the enabled channel is

performed analogous to the device mode.

 If single HS or a single LS driver is disabled, then its overload signal is not needed to create a general

overload signal, in that case just the other (enabled) HS or LS driver can generate the overload exception.

 If the die temperature exceeds the configured limit thus a temperature overload exception is detected, the

IC locks both channels and signals and according to the IC’s configuration an interrupt can be signaled at

the INT_L pin.

Device mode:

 Any single overloaded HS or LS driver of the COM or AUX channel leads to a lock and an interrupt

signaling (INT_L pin) according to the configuration of the IC.

 If the die temperature exceeds the configured limit thus a temperature overload exception is detected, the

IC locks both driver channels and signals and according to the IC’s configuration an interrupt is signaled at

the INT_L pin.

 If both drivers are configured parallel, the interrupt behavior equals the master mode

The lock mode is associated with IC-internal exceptions that are signaled to the interconnected µC as an interrupt.

The details for building and clearing an exception are described in the chapter 3.3.10 which deals with the

interrupt handling and lock mode operation.

3.3.7.

Memory Unit

The memory unit of the IC provides several IC configuration options. Those configuration options define the

properties of the Ics driver channels and define the IC monitoring and protection functions with respect to the

over-current and over-temperature handling.

12 Not applicable for the IC versions ZIOL22xx/21xx

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