AN4471 datasheet(28/39 Pages) STMICROELECTRONICS

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Connectors

AN4471

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DocID026197 Rev 1

Two right-angle, 12-pin (2 x 6 female) Peripheral module (PMOD) headers (J8, J9) are

interfaced with the FPGA, with each header providing 3.3 V power, ground and eight I/O's,

see Table 25 and Table 26. These headers may be utilized as general-purpose I/Os or may

be used to interface to PMODs to enable additional user customization. J8 and J9 are

placed in close proximity (0'9" - centers) on the PCB in order to support dual PMODs.

The STEVAL-IME009V1 evaluation board supports the serial peripheral interface (SPI

Flash) method of configuring the FPGA. The default configuration mode (determined by

pull-up/pull-down resistors R17, R18, R21, and R22) is “Master Serial / SPI” mode, which

allows the FPGA to be configured from the SPI Flash device. Spartan-6 devices have a

dedicated four-wire JTAG port (always available to the FPGA regardless of the mode pin

settings) that enables the Boundary-scan configuration method.

Configuring the FPGA via Boundary-scan requires a JTAG download cable to be attached to

the 14-pin 2 mm spaced keyed header J11 (to be mounted) with a ribbon cable. Resistors

RN1, R41 - R44 and diode D22 must also be mounted.

Jumper J13 is used to prevent FPGA programming from the configuration source. It must be

open (default) to enable FPGA programming. LED D23, labeled “DONE” on the board,

illuminates to indicate when the FPGA has been successfully configured.

Table 26. FPGA PMOD connectors (J9) not mounted on the board

Pin number

Description

Pin number

Description

Not used

GND

3.3 V

Not used

GND

3.3 V

Table 27. FPGA JTAG connectors (J11) not mounted on the board

Pin number

Description

Pin number

Description

GND

3.3 V

GND

TMS

GND

TCK

GND

TDO

GND

TDI

GND

Not used

GND

Not used

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