ISPMACH4ACPLDFAMILY datasheet(12/62 Pages) LATTICE

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ispMACH 4A Family

Note:

1. Polarity of CLK/LE can be programmed

Although the macrocell shows only one input to the register, the XOR gate in the logic allocator

allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product

terms are divided between J and K (or S and R). When conﬁgured as J-K, S-R, or T-type, the

extra product term must be used on the XOR gate input for ﬂip-ﬂop emulation. In any register

type, the polarity of the inputs can be programmed.

The clock input to the ﬂip-ﬂop can select any of the four PAL block clocks in synchronous mode,

with the additional choice of either polarity of an individual product term clock in the

asynchronous mode.

The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous

reset and preset are provided, each driven by a product term common to the entire PAL block.

Table 8. Register/Latch Operation

Conﬁguration

Input(s)

CLK/LE 1

Q+

D-type Register

D=X

D=0

D=1

0,1,

↓ (↑)

↑ (↓)

T-type Register

T=X

T=0

T=1

0, 1,

↓ (↑)

↑ (↓)

D-type Latch

D=X

D=0

D=1

1(0)

0(1)

Power-Up

Reset

D/T/L

PAL-Block

Initialization

Product Terms

a. Power-up reset

Power-Up

Preset

D/L

PAL-Block

Initialization

Product Terms

17466G-012

17466G-013

Figure 7. Synchronous Mode Initialization Conﬁgurations

b. Power-up preset

ISPMACH4ACPLDFAMILY Datasheet(PDF) 12 Page - Lattice Semiconductor

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