ISPMACH4ACPLDFAMILY datasheet(20/62 Pages) LATTICE

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ispMACH 4A Family

ispMACH 4A TIMING MODEL

The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a

ispMACH 4A device, and at the same time, be easy to understand. This model accurately

describes all combinatorial and registered paths through the device, making a distinction

between internal feedback and external feedback. A signal uses internal feedback when it is fed

back into the switch matrix or block without having to go through the output buffer. The input

switch matrix after having gone through the output buffer, it is using external feedback.

The parameter, tBUF, is deﬁned as the time it takes to go from feedback through the output buffer

to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter

designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter

is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized ispMACH 4A

timing model is shown in Figure 15. Refer to the application note entitled MACH 4 Timing and

High Speed Design for a more detailed discussion about the timing parameters.

SPEEDLOCKING FOR GUARANTEED FIXED TIMING

The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual

macrocell with the assistance of an XOR gate without incurring additional timing delays.

The design of the switch matrix and PAL blocks guarantee a ﬁxed pin-to-pin delay that is

independent of the logic required by the design. Other competitive CPLDs incur serious timing

delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and

SpeedLocking combine to give designs easy access to the performance required in today’s

designs.

(External Feedback)

(Internal Feedback)

INPUT REG/

INPUT LATCH

tSIRS

tHIRS

tSIL

tHIL

tSIRZ

tHIRZ

tSILZ

tHILZ

tPDILi

tICOSi

tIGOSi

tPDILZi

tSS(T)

tSA(T)

tH(S/A)

tS(S/A)L

tH(S/A)L

tSRR

tPDi

tPDLi

tCO(S/A)i

tGO(S/A)i

tSRi

COMB/DFF/TFF/

LATCH/SR*/JK*

S/R

BLK CLK

OUT

tPL

tBUF

tEA

tER

tSLW

Central

Switch

Matrix

*emulated

17466G-025

Figure 15. ispMACH 4A Timing Model

ISPMACH4ACPLDFAMILY Datasheet(PDF) 20 Page - Lattice Semiconductor

ISPMACH4ACPLDFAMILY Datasheet(HTML) 20 Page - Lattice Semiconductor

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