ISPMACH4ACPLDFAMILY datasheet(13/62 Pages) LATTICE

No. de pieza	ISPMACH4ACPLDFAMILY

Descripción Electrónicos	High Performance E 2 CMOS In-System Programmable Logic

PDF	62 Pages

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Fabricante Electrónico	LATTICE [Lattice Semiconductor]

Página de inicio	http://www.latticesemi.com

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13 / 62 page

ispMACH 4A Family

A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged,

providing ﬂexibility. In asynchronous mode (Figure 8), a single individual product term is

provided for initialization. It can be selected to control reset or preset.

Note that the reset/preset swapping selection feature effects power-up reset as well. The

initialization functionality of the ﬂip-ﬂops is illustrated in Table 9. The macrocell sends its data

to the output switch matrix and the input switch matrix. The output switch matrix can route this

data to an output if so desired. The input switch matrix can send the signal back to the central

switch matrix as feedback.

Note:

1. Transparent latch is unaffected by AR, AP

Table 9. Asynchronous Reset/Preset Operation

CLK/LE1

Q+

See Table 8

01X1

10X0

11X0

Power-Up

Reset

D/L/T

Individual

Reset

Product Term

a. Reset

Power-Up

Preset

D/L/T

Individual

Preset

Product Term

b. Preset

17466G-014

17466G-015

Figure 8. Asynchronous Mode Initialization Conﬁgurations

ISPMACH4ACPLDFAMILY Datasheet(PDF) 13 Page - Lattice Semiconductor