ENFALLING

START

STOP

ENRISING

ENFALLING

p

h

ENRISING

V

V

V

V

R1

V

I

1

I

V

æ

ö

-

ç

÷

è

ø

=

æ

ö

-

+

ç

÷

è

ø

EN

i1

ihys

VIN

+

–

TPS5432

R1

R2

1.2 mA

3.4 mA

REF

OUT

REF

V

R2 =

R1

V

V

´

-

VSENSE

V

O

+

–

TPS5432

R1

R2

0.808 V

TPS5432

www.ti.com

SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012

ADJUSTING THE OUTPUT VOLTAGE

The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to

use divider resistors with 1% tolerance or better. Start with a 10 k

Ω for the R1 resistor, Figure 17, and use the

Equation 1 to calculate R2. To improve efficiency at light loads consider using larger value resistors. If the values

are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are

noticeable.

Figure 17. Voltage Divider Circuit

(1)

ENABLE AND UNDERVOLTAGE LOCKOUT

The TPS5432 is disabled when the VIN pin voltage falls below 2.4V. If an application requires a higher under-

voltage lockout (UVLO), use the EN pin as shown in Figure 18 to adjust the input voltage UVLO by using two

external resistors. The EN pin has an internal pull-up current source that provides the default condition of the

TPS5432 operating when the EN pin floats. Once the EN pin voltage exceeds 1.23V, an additional 3.4µA of

hysteresis is added. When the EN pin is pulled below 1.19V, the 3.4µA is removed. This additional current

facilitates input voltage hysteresis.

If the target Vout > 2.4V, it is possible for the IC to work under 100% duty ratio without BOOT-PH voltage >

BOOT-PH UVLO threshold satisfied during power up and power down. To avoid this, it is strongly recommended

to add a resistor divider (R1 & R2 in Figure 18) at the EN pin to program VIN UVLO at a new threshold that is

higher than Vout.

Figure 18. Adjustable Under Voltage Lock Out

(2)

Copyright © 2012, Texas Instruments Incorporated

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